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1.3 7 0 6 4 SPECIFICATIONS
VXlbus Revision 1.3 compatible
CPU :
CPU Clock Rate :
Non-Volatile Memory :
RAM Memory :
ROM Memory :
Buffered I/O :
Breadboard Area :
Manufacturer ID no.:
Model no.:
Logical Addressing:
Address Space :
Device Class :
Interrupt Levels :
Trigger Levels :
Shared Memory :
Byte Available
Byte Request
Write to logical address register
Read Status Byte
Read Protocol Error
Asynchronous Mode Control
Begin Normal Operations Top
Control Response
Read Interrupter Line
1-2
IEEE 488.2 Compatible
68000
8 MHz (12.5 MHz option available)
16K expandable to 64K
64K expandable to 256K
128K expandable to 512K
96 Channels
70 Square inches
VXlbus Interface
3915 (user programmable)
3915 (user programmable)
Dynamic or Static configured (1 to 254)
Al6 (A24 on 7064-10)
Message Based Slave Device
Programmable
Programmable TTL levels
Available for 7064-10
Word Serial Protocol Supported:
Unsupported Commands
Trigger
Clear
Abort Normal Operations
Assign Interrupter Line
Begin Normal Operations
Control Event
End Normal Operations
Read Protocol
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