HP Broadband Series User Manual page 34

Coded Electrical Receiver
Clock
Data
Format
Input Signals
Equalization
Monitor Mode
Return Loss
Impedance
Protection
Connector
Rx Clock and Data
Clock
Format
Timing
Impedance
Level
Interface
Connector
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155.52 MHz with 50% ± 10% duty cycle (typical)
Serial stream: 155.52 Mb/s ± 100 ppm
CMI
STS-3 and STM-1
Automatic equalization
20 dB of fixed gain to cater for nominal monitor point loss
> 15 dB (7 MHz to 234 MHz)
Unbalanced, 75 Ω to ground (nominal)
Maximum applied voltage ± 5 V short term
BNC
155.52 MHz with 50% ± 10% duty cycle (typical)
Non-return to zero (NRZ)
Data set-up time: > 600 ps
Data hold time: > 3.12 ns
50 Ω nominal, terminated to −2 V
ECL
DC coupled
SMA
Specifications
Electrical Specifications
4-5