Marantz AV8003 Service Manual page 125

IC35 : M12L64164A7T
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
Clock
Generator
CKE
Address
Mode
Register
CS
RAS
CAS
WE
PIN FUNCTION DESCRIPTION
PIN NAME
CLK System Clock
Chip Select
CS
CKE Clock Enable
A0 ~ A11 Address
A12 , A13 Bank Select Address
Row Address Strobe
RAS
Column Address Strobe
CAS
Write Enable
WE
L(U)DQM Data Input / Output Mask
DQ0 ~ DQ15 Data Input / Output
VDD / VSS Power Supply / Ground
VDDQ / VSSQ Data Output Power / Ground
NC No Connection
Elite Semiconductor Memory Technology Inc.
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Data Control Circuit
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
161
M12L64164A
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
INPUT FUNCTION
after the clock and masks the output.
SHZ
Publication Date: Jul. 2005
Revision: 2.4
L(U)DQM
DQ
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