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The 12-position DIP switch (SW1) is used to configure the S1D13709 for different host bus
interfaces and for TFT panel or STN panel for TFT-LCD Automatic Setting Mode.
S5U13709P00C100
S1D13709
SW1-[12:1]
Configuration
SW1-[12]
TESTEN
SW1-[11]
CNF10
SW1-[10]
CNF9
SW1-[9]
CNF8
SW1-[8:6]
CNF[7:5]
SW1-[5]
CNF4
SW1-[4:3]
CNF[3:2]
SW1-[2:1]
CNF[1:0]
= default setting
7
EPSON
Table 3-1a: Summary of Configuration Options
Pin
CLKI (XCG1) frequency is 24MHz
This setting is available only when the TFT-LCD Automatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
TFT Interface Output Drive is 6mA@3.3V
(8mA@5V)
This setting is available only when the TFT-LCD Automatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
All output video signals change at rising edge
of FPSHIFT
This setting is available only when the TFT-LCD Automatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
CNF7 CNF6 CNF5 TFT-LCD Automatic Setting Mode
0
0
0
Disable (Manual setting)
S1D13700 S/W: QVGA → TFT: QVGA
0
0
1
S1D13700 S/W: QVGA → TFT: WQVGA
0
1
0
S1D13700 S/W: QVGA → TFT: VGA
0
1
1
S1D13700 S/W: QVGA → TFT: WVGA
1
0
0
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
When the STN interface is used (REG[34h] bit0 = 0), CNF[7:5]
should be 000.
Indirect Addressing Mode:
1-bit address bus, 8-bit data bus
9pin are used
Select the host bus interface as follows:
CNF3 CNF2 Host Bus
0
0
Generic Bus
0
1
Reserved
1
0
M6800 Family Bus Interface
1
1
MC68K Family Bus Interface
Select the XSCL cycle time (XSCL:CLOCK
Input) as follows:
For 1bpp mode (REG[20h] bit 1-0 = 00)
CNF1 CNF0 XSCL Cycle Time
0
0
4:1
0
1
8:1
1
0
16:1
1
1
Reserved
For 2bpp mode (REG[20h] bit 1-0 = 01)
CNF1 CNF0 XSCL Cycle Time
0
0
8:1
0
1
16:1
1
0
32:1
1
1
Reserved
For 4bpp mode (REG[20h] bit 1-0 = 10)
CNF1 CNF0 XSCL Cycle Time
0
0
16:1
0
1
32:1
1
0
64:1
1
1
Reserved
When the TFT Interface is used (REG[34h] bit0 = 1), CNF[1:0]
should be 00.
S5U13709P00C100 Evaluation Board User Manual Rev. 1.00
S5U13709 Evaluation Board User Manual
Configuration State
1 (ON)
Not use
0 (OFF)
Normal use "GND"
CLKI (XCG1) frequency is 20MHz
TFT Interface Output Drive is 2mA@3.3V
(3mA@5V)
All output video signals change at the
falling edge of FPSHIFT
TFT interface is used. (TFT-LCD Automatic
Setting Mode Disable)
Or STN interface is used. (REG[34h] bit0
= 0)
Direct Addressing Mode:
16bit address bus, 8-bit data bus
24pin are used.
Select the host bus interface as "Generic
Bus".
For 1bpp mode (REG[20h] bit 1-0 = 00)
CNF1 CNF0 XSCL Cycle Time
0
0
4:1
For 2bpp mode (REG[20h] bit 1-0 = 01)
CNF1 CNF0 XSCL Cycle Time
0
0
8:1
For 4bpp mode (REG[20h] bit 1-0 = 10)
CNF1 CNF0 XSCL Cycle Time
0
0
16:1
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