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Falling-Edge Detection Registers (Ports 0–2)
These registers enable edge detection interrupts for falling edges on selected lines of input
ports. To generate interrupts you must also set the EdgeInt bit in the Master Interrupt Control
Register.
Address Offsets:
Type:
Size:
Bit Map:
7
6
Fall.7
Fall.6
Bit
7–1
© National Instruments Corporation
20 (hex) for Port 0
21 (hex) for Port 1
22 (hex) for Port 2
Read and write
8-bit
5
4
Fall.5
Fall.4
Name
Description
Fall.<7..0>
Falling-Edge Detection enables—Each bit enables
interrupt generation on falling edges of the corresponding
input line.
1 = Falling-edge detection enabled
0 = Falling-edge detection disabled
Chapter 2
3
2
Fall.3
Fall.2
2-13
6527 Register-Level Programmer Manual
Register Map and Descriptions
1
0
Fall.1
Fall.0
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