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Chapter 2
timebase clocks can be used as counting sources, and these clocks have a maximum skew of
75 nsec between them. The SOURCE signal shown in Figure 2-9 represents any of the signals
applied at the SOURCE inputs, GATE inputs, or internal timebase clocks. See the Am9513A
data sheet in Appendix C for further details.
Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or
one of the Am9513A internally generated signals. Figure 2-9 shows the GATE signal referenced
to the rising edge of a source signal. The gate must be valid (either high or low) at least 100 nsec
before the rising or falling edge of a source signal for the gate to take effect at that source edge
(as shown by t
and t
gsu
nsec after the rising or falling edge of a source signal for the gate to take effect at that source
edge. The gate high or low period must be at least 145 nsec in duration. If an internal timebase
clock is used, the gate signal cannot be synchronized with the clock. In this case, gates applied
close to a source edge take effect either on that source edge or on the next one. This arrangement
creates an uncertainty of one source clock period with respect to unsynchronized gating sources.
Signals generated at the OUT pin are referenced to the signal at the SOURCE input or to one of
the Am9513A internally generated clock signals. Figure 2-9 shows the OUT signal referenced to
the rising edge of a source signal. Any OUT signal state changes occur within 300 nsec after the
source signal's rising or falling edge.
Digital I/O Signal Connections
Pins 31, 32, and 35 through 50 of the I/O connector are digital I/O signal pins.
Pins 35 through 42 are connected to the digital lines A<0..7> for digital I/O Port A. Pins 43
through 50 are connected to the digital lines B<0..7> for digital I/O Port B. Pins 31 and 32 are
connected to the external interrupt lines, EXTIRQ1 and EXTIRQ2. Ports A and B can be
programmed on a bitwise basis to be inputs or outputs.
The following specifications and ratings apply to the digital I/O lines.
Absolute maximum voltage rating
Digital Input Specifications (referenced to GND):
Input logic high voltage
Input logic low voltage
Input current, Port A
(0 < V in < 0.8 V)
Input current, Port A
(2.0 < V in < 5.25 V)
Input current, Port B
(0.4 < V in < 2.4 V)
Input current, EXTIRQ1 and EXTIRQ2
(0 < V in < 5.25 V)
© National Instruments Corporation
in Figure 2-9). Similarly, the gate signal must be held for at least 10
gh
-0.3 to +7.0 V with respect to GND
Minimum
2.0 V
0.0 V
–
-400 µA
–
–
–
2-13
Configuration and Installation
Maximum
5.25 V
0.8 V
-2.4 mA
10 µA
2.5 µA
PC-TIO-10 User Manual
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