The External Reference Divider; The Dac - RF Technology Eclipse Series Operation And Maintenance Manual

5 CIRCUIT DESCRIPTION
The FoLD pin, of U604, can be used for many purposes. It can be connected to the
output of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or as
a user programmable output pin. In this circuit it is used as a LOCK-DETECT output
when the frequency is being changed, but otherwise it is connected internally to the
unused reference divider of U604, to deliver a 400Hz pulse train to FoLD.
U604 is set up with a phase detector frequency of 31.25kHz.
The signal CHAN_VCO_EN is an output from the CPU that is used to turn on (when
High) or turn off (when low) the Channel VCO.

5.6.3 The External Reference Divider

The external Reference Input (EXT_REF_IN) is buffered by an attenuator network
formed by R628,R633, and R630 in parallel with R635. This also forms a 50 ohm
termination network for the reference input.
R628 is a 1 watt resistor, and so, in theory levels as high as +30dBm can be accepted.
To be safe, though, the largest signal that is approved to be accepted is +26dBm.
Q600 is set up as a switching transistor, and with a sufficiently high input signal level (>
+5dBm), it will clock U605.
U605 is set up as a divide by 128 circuit, and its output is then divided by U606 by 25.
The two unused, divide by two, stages of U606 are then used to convert the 400Hz
FoLD pulse trains into 200Hz square waves for the Timer inputs of the CPU.

5.6.4 The DAC

U601 is a quad DAC. It is programmed by the CPU via the serial bus (SCLK and
MOSI). It is selected by the low active signal SIGGEN_ADSEL.
Three of its outputs are used to adjust the reference oscillators.
In the presence of a GPS 1Hz pulse input, or an external reference oscillator, the
software will automatically track the channel VCO to these external inputs. (GPS has
priority over an external reference).
The modulation reference oscillator is always tracked as closely as possible to the
Channel reference oscillator. Because of this need for very close tracking, two DAC
outputs are summed. In this way, the CPU is given coarse, as well as fine control.
The CPU can sense a phase difference of 136ns in 4 seconds, i.e. as little as 0.034ppm
between the two PLL reference oscillators. Each step of the MOD_ADJ_FINE DAC
output will move the frequency about one eighth of this amount.
The other DAC output (BALANCE) is used to adjust the BALANCE VCA (see sheet
7).
RF Technology T50 Page 23