RF Technology Eclipse Series Operation And Maintenance Manual page 15

5 CIRCUIT DESCRIPTION
FRDY is an output from the flash. It goes low when the Flash starts to write a byte of
data, or erase a block, or erase the whole chip, and it returns to its default high state
when the action requested has completed.
FPSW1 is the switch input from the PTT Test pin.
FPSW2, and FPSW3 are two pins that have been reserved for future use as switch
inputs.
LOOP/VOLTS_SEL is a CPU output that when high applies 12V of dc feed to the
audio output.
TONE_DEV_U/D and TONE_DEV_INC are CPU outputs that are used to control the
digital potentiometer that sets the TONE deviation level. (see 5.5)
EXT_TONE_SEL is a CPU output that when low enables differential analogue input
from the TONE+/TONE- pair. (see 5.5)
LINEINP_ADSEL is a serial bus select pin. It selects the quad Digital to Analogue
converter (DAC) that sets the levels for the two Line input Voltage Controlled
Amplifiers, the output RF power amplifier bias voltage, and the LCD bias circuit. (see
5.4)
LINEINP_DSEL is also a serial bus select pin. It is used to select the shift register that
is used to control most of the analogue switches in the audio Line input circuitry, as
well as the digital POT used to set the maximum deviation level. (See 5.4)
PWR_CNTRL_HIGH is a CPU output that can be low, tri-state, or high. This adjusts,
slightly, the range of the power amplifier bias circuitry allowing finer control of the
output power level. (see 5.4 and 5.8)
CTCSS_SEL is a serial bus select pin. It is used to select the FX805 chip(U500), which
is used to generate CTCSS tones. (see 5.5)
CHAN_PLL_SEL is a serial bus select pin. It is used to select the PLL chip in the
Channel PLL circuit (U604). (See 5.6)
SIGGEN_ADSEL is a serial bus select pin. It is used to select the quad DAC in the RF
area. This DAC controls the reference oscillator bias voltages, and the BALANCE
voltage controlled amplifier. (See 5.6)
CHAN_VCO_EN is a CPU output that enables (when high) the Channel VCO. (See 5.6
and 5.7)
EXT_REF_DIV is a CPU timer input. It is the output of the external reference clock
divided by 3200. The software can measure what the reference frequency is, and then
use this input to calculate the frequency error of the channel PLL reference oscillator. It
can then adjust the channel reference oscillator to reduce this error to less than 0.3ppm.
(See 5.6)
RF Technology T50 Page 15