Microprocessor (Sheet 2) - RF Technology Eclipse Series Operation And Maintenance Manual

Note that the external reference frequency is limited to:
500kHz, or any multiple
any multiple of 128KHz greater than or equal to 4
any multiple of 160KHz greater than or equal to 3
P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminal
emulator, or to an IBM PC running the Eclipse50 software.
JP2 is for the attachment of an LCD display module. This has been included for later
development.
JP3 is a specialised connector for test and factory configuration use only.
RV100 represents the front panel LINE potentiometer.
SW1 represents the PTT test pin.
D102, D103, and D104 represent the three front panel LEDs.
5.2

Microprocessor (Sheet 2)

Sheet 2 describes the basic microprocessor circuitry.
The core CPU is the Motorola XC68HC12A0. It is configured in 8 bit data width
mode.
The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising the
JFET Q202, and two switching transistors Q203 and Q204.
The CPU contains an 8 channel A/D converter whose inputs are identified as AN0,
AN1, ..., AN7.
AN7 and AN6 are used as LOCK detect inputs from the two Phase Locked Loop (PLL)
circuits (see 5.6)
AN5 is used to sense whether or not the dc supply is within spec or not.
AN4 is multiplexed between the LINE control potentiometer and the Channel reference
crystal's temperature sense. Which analogue input drives this analogue input, is defined
by the state of TEMP_LEVEL_IN which is a CPU output signal.
AN3 and AN1 are inputs from the PLL circuits that sense the bias voltage on the VCO
control varactor for each VCO.
AN2 is used to sense the average peak voltage of the audio input.
AN0 is used to sense the average peak voltage of the RF output.
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5 CIRCUIT DESCRIPTION
RF Technology T50