Table of Contents
Advertisement
October 9th, 1995
C. DCU (DATA COMPRESSION UNIT)
C.1. OVERVIEW
The DCU receives scanned images in binary video data form from the image
processor (SIP3) on the SCU board and compresses the data using MH, MR,
or MMR, whichever is selected. The DCU sends the compressed data to the
SBC (Scan Buffer Controller) on the SCU board.
C.2. FEATURES
For high speed processing, the input/output data processing in the DCU is
16-bit. To make the DCU compact, the FPGA is used for both data input and
output processing.
C.3. BLOCK DIAGRAM
A0 - A7
D0 - D7
SBC
DRAM
4 Mbits x 2
Address
Decoder
VDATA0 - VDATA7
8-bit to 16-bit
Converter
Selector
FIFO 1
5k x 8 bits
FIFO 2
5k x 8 bits
I/O Controller
(FPGA)
Function
Register
C-1
DCU (DATA COMPRESSION UNIT)
8-bit to 16-bit
Selector
Converter
DICEP-E1
OVERVIEW
VIDEO I/F
G404O501.WMF
Advertisement
Table of Contents
