1. Manuals
  2. Brands
  3. Abatron Manuals
  4. Recording Equipment
  5. bdiGDB
  6. User manual

Abatron bdiGDB User Manual

Jtag debug interface for gnu debugger arm11 / cortex
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
GDB
bdi
JTAG debug interface for GNU Debugger
ARM11 / Cortex
User Manual
Manual Version 1.21 for BDI2000
©1997-2014 by Abatron AG

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the bdiGDB and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Abatron bdiGDB

Summary of Contents for Abatron bdiGDB

  • Page 1 JTAG debug interface for GNU Debugger ARM11 / Cortex User Manual Manual Version 1.21 for BDI2000 ©1997-2014 by Abatron AG...

  • Page 2: Table Of Contents

    3.5 Multi-Core Support....................... 52 4 Specifications ..........................55 5 Environmental notice........................ 56 6 Declaration of Conformity (CE)....................56 7 Abatron Warranty and Support Terms ..................57 7.1 Hardware ..........................57 7.2 Software ..........................57 7.3 Warranty and Disclaimer ..................... 57 7.4 Limitation of Liability ......................
  • Page 3 GNU Debugger, BDI2000 (ARM11 / Cortex) User Manual Appendices A Troubleshooting ........................58 B Maintenance ..........................59 C Trademarks ..........................60 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 4: Introduction

    Ethernet (10 BASE-T) 1.1 BDI2000 The BDI2000 is the main part of the bdiGDB system. This small box implements the interface be- tween the JTAG pins of the target CPU and a 10Base-T ethernet connector. The firmware and the programable logic of the BDI2000 can be updated by the user with a simple Windows / Linux config- uration program.

  • Page 5: Bdi Configuration

    BDI2000. Every time the BDI2000 is powered on, it reads the configuration file via TFTP. Following an example of a typical configuration file: ; bdiGDB configuration for ARM Integrator CM1136JF-S ; -------------------------------------------------- [INIT]...

  • Page 6: Installation

    14 - NC 20 - NC The green LED «TRGT» marked light up when target is powered up For BDI MAIN / TARGET A connector signals see table on next page. © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 7 For targets with a 10-pin or 20-pin Cortex Debug Connector (Samtec 0.05" micro header) a special adapter is available. This Cortex Adapter can be ordered separately from Abatron (p/n 90085). For targets with a 14-Pin TI connector, a special cable is available. This cable can be ordered sep- arately from Abatron (p/n 90053).

  • Page 8: Changing Target Processor Type

    For more information about adaptive clocking see ARM documentation. Note: Adaptive clocking is only supported with BDI2000 Rev.B/C and a special target cable. This special cable can be ordered separately from Abatron (p/n 90052). Rev. B/C 20 pin Multi-ICE...
  • Page 9 This output of the BDI2000 connects to the target TMS line. reserved reserved GROUND System Ground RESET System Reset This open-drain output of the BDI2000 is used to reset the target system. reseved reseved GROUND System Ground © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 10: Serial Wire Debug

    This input to the BDI2000 is used to detect if the target is powered up. If there is a current limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less. © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 11: Connecting The Bdi2000 To Power Supply

    The BDI2000 needs to be supplied with 5 Volts (max. 1A) via the POWER connector. The available power supply from Abatron (option) or the enclosed power cable can be directly connected. In order to ensure reliable operation of the BDI2000, keep the power supply cable as short as possible.

  • Page 12: Status Led "Mode

    The BDI is ready for use, the firmware is already loaded. The power supply for the BDI2000 is < 4.75VDC. BLINK The BDI «loader mode» is active (an invalid firmware is loaded or loading firmware is active). © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 13: Connecting The Bdi2000 To Host

    2.4 Connecting the BDI2000 to Host 2.4.1 Serial line communication Serial line communication is only used for the initial configuration of the bdiGDB system. The host is connected to the BDI through the serial interface (COM1...COM4). The communication cable (included) between BDI and Host is a serial cable. There is the same connector pinout for the BDI and for the Host side (Refer to Figure below).

  • Page 14: Ethernet Communication

    When this LED light BLINKS, data is being transmitted through the UTP port of the BDI2000 Receive When this LED light BLINKS, data is being received through the UTP port of the BDI2000 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 15: Installation Of The Configuration Software

    The MAC address is derived from the serial number as follows: MAC: 00-0C-01-xx-xx-xx , repace the xx-xx-xx with the 6 left digits of the serial number Example: SN# 93123457 ==>> 00-0C-01-93-12-34 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 16: Configuration With A Linux / Unix Host

    [root@LINUX_1 bdisetup]# ./bdisetup -u -p/dev/ttyS0 -b57 -aGDB -tARM11 Connecting to BDI loader Erasing CPLD Programming firmware with ./b20armgd.103 Programming CPLD with ./armjed21.102 Note: for Serial Wire Mode use -tARMSWD instead of -tARM11 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 17 BDI, wait some time (1min.) and power-on it again to exit loader mode. [root@LINUX_1 bdisetup]# ./bdisetup -v -p/dev/ttyS0 -b57 -s BDI Type : BDI2000 Rev.C (SN: 92152150) Loader : V1.05 Firmware : V1.03 bdiGDB for ARM11 Logic : V1.02 ARM : 00-0c-01-92-15-21 IP Addr : 151.120.25.101...

  • Page 18: Configuration With A Windows Host

    This button is only active if there is a newer firmware or logic version pres- ent in the execution directory of the bdiGDB setup software. Press this but- ton to write the new firmware and/or logic into the BDI2000 flash memory / programmable logic.

  • Page 19: Recover Procedure

    • Switch ON the power supply for the BDI again and wait until the LED «MODE» blinks fast DEFAULT • Turn the power supply OFF again • Return the jumper to the «DEFAULT» position • Reassemble the unit as described in Appendix «Maintenance» © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 20: Testing The Bdi2000 To Host Connection

    [p] [w] [dRootDirectory] Without any parameter, the server starts in read-only mode. This means, only read access request from the client are granted. This is the normal working mode. The bdiGDB system needs only read access to the configuration and program files.

  • Page 21: Using Bdigdb

    Numeric parameters can be entered as decimal (e.g. 700) or as hexadecimal (0x80000). The core# is optional. If not present the BDI assume core #0. See also chapter "Multi-Core Support". © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 22: Part [Init]

    WAPB address value Cortex-A: Write a word (32bit) to the Debug APB memory. address the APB memory address value the value to write to the APB memory Example: WAPB 0xd4012014 0x08000014 ; RCSR © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 23 CLOCK entry in the [TARGET] section. This entry maybe of in- terest to speed-up JTAG clock as soon as possible (after PLL setup). value see CLOCK parameter in [TARGET] section Example: CLOCK 2 ; switch to 8 MHz JTAG clock © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 24 Therefore it is possible first to enable some RAM with the init list before the startup code is loaded and executed. [INIT] WM32 0x0B000020 0x00000000 ;Clear Reset Map FILE d:\gdb\bdi\startup.hex FORMAT SREC START 0x100 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 25: Part [Target]

    4 = 1 MHz 9 = 20 kHz 5 = 500 kHz 10 = 10 kHz Example: CLOCK 2 ; 16 MHz JTAG clock CLOCK 8000000 ; 8 MHz JTAG clock © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 26 This delay is necessary when a target needs some wake-up time after a reset. time the delay time in milliseconds Example: WAKEUP 3000 ; insert 3sec wake-up time © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 27 This way we step over excep- tions. INTO In this mode, the BDI sets a hardware breakpoint on all addresses except the current instruction address. This way we step into exceptions. Example: STERPMODE INTO © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 28 APB memory space. Otherwise it defines an ICEPick register. address APB address or ICEPick register block/number Example: DAPPC 0xD4159008 ;DAP-PC Cortex-A9#0 DAPPC 0xD415900C ;DAP-PC Cortex-A9#1 DAPPC 0x60 ;non-JTAG register 0 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 29 (IR). Example: SCANSUCC 2 12 ; two device with an IR length of 8+4 Note: For Serial Wire Mode, the following parameters are not relevant, have no function: TRST, SCANPRED, SCANSUCC © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 30 Check if debug module is accessible If (startup == reset) catch reset exception If (reset mode == hard) Release reset Wait until reset is really release Execute SCANPOST string Delay for wake-up time © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 31: Part [Host]

    TCP/IP connection (Telnet/GDB) will be closed if there is a connect request from the same host (same IP address). port the TCP port number (default = 2001) Example: DEBUGPORT 2001 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 32 If it should not send echoes and let the Telnet client in "line mode", add this entry to the configuration file. mode ECHO (default), NOECHO or LINE Example: TELNET NOECHO ; use old line mode © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 33: Part [Flash]

    User Manual 3.2.4 Part [FLASH] The Telnet interface supports programming and erasing of flash memories. The bdiGDB system has to know which type of flash is used, how the chip(s) are connected to the CPU and which sectors to erase in case the ERASE command is entered without any parameter.
  • Page 34 ;erase sector 5 of flash SIMM ERASE 0x04018000 ;erase sector 6 of flash SIMM ERASE 0x0401C000 ;erase sector 7 of flash SIMM the above erase list maybe replaced with: ERASE 0x04000000 0x4000 8 ;erase 8 sectors © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 35 ;USECRL: Flash USec Reload for 50 MHz [FLASH] WORKSPACE 0x20000000 ;workspace in internal SRAM CHIPTYPE LM3S CHIPSIZE 0x40000 BUSWIDTH FILE E:/temp/dump16k.bin FORMAT BIN 0x00030000 ERASE 0x00030000 0x400 16 Mass erase via Telnet: BDI> erase 0x00000000 mass © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 36 0xFF. Following an example how to erase the complete flash via Telnet: For SAM3U4: BDI> erase 0x00080000 block BDI> erase 0x00100000 block For SAM3S4: BDI> erase 0x00400000 block © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 37 The BDI supports programming of the Energy Micro EFM32 internal flash memory. [FLASH] CHIPTYPE EFM32 CHIPSIZE 0x20000 ;128 kB FLASH FILE E:/temp/dump16k.bin FORMAT BIN 0x00010000 ERASE 0x00010000 512 ;erase 32 x 512 byte pages © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 38 ;erase 16 kB sector ERASE 0x0800C000 ;erase 16 kB sector ERASE 0x08010000 ;erase 64 kB sector ERASE 0x08020000 0x20000 7 ;erase all 7 128 kB sectors Mass erase via Telnet: BDI> erase 0x08000000 mass © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 39 The flash type selects the appropriate algo- rithm and gives additional information about the used flash. On our web site (www.abatron.ch -> Debugger Support -> GNU Support -> Flash Support) there is a PDF document available that shows the supported parallel NOR flash memories.
  • Page 40 The following example unlocks all 256 sectors of an Intel Strata flash ( 28F256K3) that is mapped to 0x00000000. In case there are two flash chips to get a 32bit system, double the "step" parameter. BDI> unlock 0x00000000 0x20000 256 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 41: Part [Regs]

    "addr" and then the register value is access using "data" as address. addr the address of the Address register data the address of the Data register Example: IMM1 0x04700000 0x04700004 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 42 0xd4011fc8 ;Device Identifier devtype 0xd4011fcc ;Device type ; 64-bit wide CP15 registers ttbr0_64 CP15 0x0002 ;Translation Table Base 0 ttbr1_64 CP15 0x0012 ;Translation Table Base 1 par_64 CP15 0x0007 ;Physical Address © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 43: Debugging With Gdb

    GDB sometimes fails to connect to the target after a reset because it tries to read an invalid stack frame. With the following init list entries you can work around this GDB startup problem: WGPR 0x00000020 ;set frame pointer to free RAM WM32 0x00000020 0x00000028 ;dummy stack frame © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 44: Breakpoint Handling

    The BDI supports the GDB V5.x "monitor" command. Telnet commands are executed and the Telnet output is returned to GDB. (gdb) target remote bdi2000:2001 Remote debugging using bdi2000:2001 0x10b2 in start () (gdb) monitor md 0 1 00000000 : 0xe59ff018 - 442503144 © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 45: Target Serial I/O Via Bdi

    Once SIO is enabled, connecting with the setup tool to update the firmware will fail. In this case either disable SIO first or disconnect the BDI from the LAN while updating the firmware. © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 46: Target Dcc I/O Via Bdi

    "mrc p14, 0, %0, c0, c1\n" : "=r" (ret)); return ret; void write_dcc_char(unsigned int c) while(read_dscr() & DSCR_WDTR_FULL); write_dtr(c); unsigned int read_dcc_char(void) while(!(read_dscr() & DSCR_RDTR_FULL)); return read_dtr(); void write_dcc_string(const char* s) while (*s) write_dcc_char(*s++); © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 47: Target Serial Wire Output Via Bdi

    + ((uint32)(*(s+2)) << 16) + ((uint32)(*(s+3)) << 24); s += 4; } /* if */ else { SWO1 = *s++; } /* else */ } /* while */ } /* SWO_WriteString */ © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 48: Telnet Interface

    During debugging with GDB, the Telnet is mainly used to reboot the target (generate a hardware re- set and reload the application code). It may be also useful during the first installation of the bdiGDB system or in case of special debug needs.

  • Page 49: Command List

    ( 8bit access)", "BDM [R|W] <addr> [<mask>] Cortex-A: set data watchpoint with address mask", "CD [<id>] clear data watchpoint(s)", "INTDIS disable target interrupts while running", "INTENA enable target interrupts while running (default)", © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 50 "-------------------------------------------", "RDP <addr> display Debug Port (DP) register", "RAP <addr> display Access Port (AP) register", "WDP <addr> <value> modify Debug Port (DP) register", "WAP <addr> <value> modify Access Port (AP) register", © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 51: Cpxx Registers

    To access 64-bit CPxx registers, define it in the register definition file and then use the Telnet rd/rm commands. The number selects the CPxx register. This number is used to build the appropriate MCRR or MRRC instruction. +-------+-------+-------+-------+ | opc1 +-------+-------+-------+-------+ © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 52: Multi-Core Support

    User Manual 3.5 Multi-Core Support The bdiGDB system supports concurrent debugging of up to 8 cores. For every core you can start its own GDB session. The default port numbers used to attach the remote targets are 2001 ... 2008. In the Telnet you switch between the cores with the command "select <0..7>".
  • Page 53 - TARGET: core #2 has entered debug mode - TARGET: core #3 has entered debug mode IMX6#0>stat Core#0: halted 0x0090013c Breakpoint Core#1: halted 0x00900120 EDBGRQ signal Core#2: halted 0x00900120 EDBGRQ signal Core#3: halted 0x00900130 EDBGRQ signal © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 54 GDB session (cores) before entering the continue command in the master GDB ses- sion. For the master core define the CGROUP mask with all cores. For other cores set only the bit in the core mask that represents the core itself. © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 55: Specifications

    -20 °C ... +65 °C Relative Humidity (noncondensing) <90 %rF Size 190 x 110 x 35 mm Weight (without cables) 420 g Host Cable length (RS232) 2.5 m Specifications subject to change without notice © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 56: Environmental Notice

    GNU Debugger, BDI2000 (ARM11 / Cortex) User Manual 5 Environmental notice Disposal of the equipment must be carried out at a designated disposal site. 6 Declaration of Conformity (CE) © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

  • Page 57: Abatron Warranty And Support Terms

    7 Abatron Warranty and Support Terms 7.1 Hardware ABATRON Switzerland warrants that the Hardware shall be free from defects in material and work- manship for a period of 3 years following the date of purchase when used under normal conditions.
  • Page 58 Network processes do not function (loading the firmware was successful) Possible reasons • The BDI2000 is not connected or not correctly connected to the network (LAN cable or media converter) • An incorrect IP address was entered (BDI2000 configuration) © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 59 2.2 Remove the two screws that hold the front panel TRGT MODE BDI MAIN BDI OPTION 3.1 While holding the casing, remove the front panel and the red elastig sealing casing elastic sealing front panel © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...
  • Page 60 Observe precautions for handling (Electrostatic sensitive device) Unplug the cables before opening the cover. Use exact fuse replacement (Microfuse MSF 1.6 AF). C Trademarks All trademarks are property of their respective holders. © Copyright 1997-2014 by ABATRON AG Switzerland V 1.21...

Table of Contents