Control And Status Register (Csr) - GE VMIVME-2533 Series Hardware Reference Manual

Differential digital output board

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VMIVME-2533 Differential Digital Ouput Board

Control and Status Register (CSR)

The CSR is a register that controls the Test Mode (TM) bits and the front panel Fail

LED as shown in Figure 1-1 on page 16. Clearing both TM1 and TM2 disables the

output differential line drivers but enables the internal data registers for off-line

Built-in-Test. Setting TM1 to a logic "1", enables the output differential line drivers.

These outputs can be read by differential line receivers for on-line Built-in-Test when

TM1 is high.

The CSR address is selected by the address jumpers JC and JE. The format of the CSR

data and address is shown in Table 3-1 on page 33. The CSR is initialized active upon

system reset such that the outputs are disabled and the front panel LED is

illuminated. Jumper JA can be used by the user for some automatic system

set-up/configuration. This nibble is part of the CSR and is available to the user for this

purpose.

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