Casio SF-8500 Service Manual & Parts List page 21

10) Power supply for LCD
(Pin69)
INT1
CPU
HD62076C02
When the system is start up, CPU will send "H" signal to VIN terminal of gate array from V2ON termi-
nal. Then, gate array will send "H" signal from VOT terminal to release interruption signal INT1 of CPU
and also, it will be sent to PDB terminal of power supply chip to generate LCD drive voltages.
11) ROM driving transistor
(Pin39)
" L "
VOB
GATE ARRAY
µ
PD65005GC-566-3B6
RSO
(Pin49)
"Pulse"
After gate array send VOT signal, gate array send "L" signal from VOB terminal to base terminal of
transistor Q1. Then, the VDD is applied to ROM (operation program), CPU can read a ROM program
data.
"H"
V2ON
(Pin45) (Pin31)
VDD
(Pin3)
R10
Transistor Q1
(Pin2)
2SA1411
(Pin1)
(Pin32)
VDD
"Pulse"
OEO
(Pin43) (Pin24)
(Pin22)
— 20 —
"H"
(Pin32)
VOT
POWER SUPPLY CHIP
VIN
GATE ARRAY
µ
PD65005GC-566-3B6
VCC
ROM
µ
PD23C4001
DATA
EBGW-304
OEB
ADDRESS
CEB
(Pin31)
PDB
SC371015FU
LCD drive voltages
VREG,V1~V4
CPU
HD62076C02