Casio SF-8500 Service Manual & Parts List page 20

8) Gate array
GND
TO MAIN SWITCH
" L "
SWO
(Pin 40)
" H " LSO
(Pin 27)
TO CPU
INT0 terminal
(Pin 70)
9) Main switch and power on switch
(Pin54)
When the main switch is set to on position, SW terminal of CPU becomes "L", then CPU will send "L"
signal to KAC terminal to enable the system power on. The KI0 terminal is "H" when VDD is applied to
CPU. Therefore, when pressing the power on switch, CPU will generate a clock pulse (2 MHz) for start
up the system.
Open
(Pin 26) (Pin 25)
LSI MON
GATE ARRAY
µ
PD65005GC-566-3B6
(Pin 7)
(Pin 33)
(Pin 34) CSB
(Pin 24)
" H "
VDD GND FROM CPU
CS2 terminal (Pin 28)
(Pin36)
SW
"L"
CPU
HD62076C02
KAC KIO
(Pin53)
"H"
"L"
POWER ON SWITCH
— 19 —
When VDD is applied from power supply IC
SC371015FU to gate array µPD65005GC-556-
3B6, gate array will send "L" signal to active the
main switch signal from terminal SWO.
Also, gate array will send "H" signal to release
the INT0 terminal of CPU from LSO terminal.
The terminal CSB is for the chip select of gate
array. This signal is sent from CPU terminal
CS2. And when the VDD is applied to CPU, CPU
will send "H" signal to CSB terminal.
VDD
MAIN SWITCH
OFF
GATE ARRAY
ON
(Pin40)
SWO
"L"
µ
PD65005GC-566-3B6