Circuit Explanations; System Chart - Casio SF-8500 Service Manual & Parts List

10. CIRCUIT EXPLANATIONS

10-1. System chart

Generally, SF-8500 is working with the following steps.
12
Power supply chip
SC371015FU
VREG,V1~V4
Output
GND VDD2
for LCD
(Pin32)
(Pin22)
driver
VDD
(Pin69)
INIT1
VDD1
GND
KAC KIO
(Pin54)
(Pin53)
"L"
7
8
1. Supply 5V to VDD1 and VDD2.
2. Output VDD (4.5V).
3. Output "L" from SWO terminal.
4. Output "H" from LSO terminal.
5. Main switch ON.
6. Input "L" to SW terminal.
7. Output "L" from KAC terminal.
8. Push power on button switch.
9. CPU oscillation is generated.
10. Output "H" from V2ON terminal.
(Pin31)
2
PDB
VDD
(Pin2)
VO1
(Pin1)
VDD1
1
(Pin19)
Power supply
Circuit
"H"
2 MHz
9
10
(Pin41)
(Pin45) (Pin40)
V2ON OSCI OSCO
(Pin70)
INT0
CPU
MAIN SWITCH
SW
(Pin36)
HD62076C02
6
"H"
ADDRESS BUS
DATA BUS
— 15 —
VDD
11
"H"
(Pin32) (Pin34)
VOT VDD GND
Gate array
µ
MON
PD65005GC-566-3B6
VOB
(Pin31)
VIN
RSO
LSO OEO
SWO
(Pin40)
(Pin27) (Pin43)
3 15
4
"L"
"H" "L"
VDD
OFF
ON
5
(Pin24)
"L"
OE
µ
17
ADDRESS
DATA
18
11. Output "H" from VOT terminal.
12. Output all LCD drive voltages.
13. Output "L" from VOB terminal.
14. Apply VDD to ROM.
15. Gate array sends ROM output
enable signal from OE terminal.
16. Gate array sends ROM Chip enable
enable signal from CE terminal.
17. CPU sends address to ROM.
18. CPU receives data from ROM.
(Pin7)
(Pin33)
VDD
(Pin26)
LSI
(Pin25)
(Pin39)
ON
(Pin49)
16
13
"L" "L"
(Pin2)
VDD
(Pin1)
Transistor Q1
(Pin3)
14
"H"
(Pin22)
VCC GND
CE
ROM
(Operation program)
PD23C4001EBGW-304