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Teledyne LeCroy
4.2
Probed Signal Electrical Requirements
The probe requires the following minimum differential signal requirements at a given bit
error rate at the analyzer probe point:
Figure 4.9: Signal Requirements for MidBus Probe
4.3
Overview of Probe - Pin Assignments
Cross‐references from the PCI Express Mid‐Bus Probing Footprint and Pinout (8/05/03)
Revision 1.0 are given in tables listed below.
The Summit T3‐16 PCI Express analyzers from Teledyne LeCroy support a lane swizzling
feature which allows pairs of differential pin assignments to be re‐wired dynamically to
match the configuration under the probe. This also provides additional versatility in the
case where two busses are mapped to the probe footprint and cannot be uniquely
positioned within a quadrant. Lane swizzling allow you to reorder upstream lanes or
recorder downstream lanes regardless of the order of physical connections – however,
you cannot interchange upstream lanes with downstream lanes.
In the pinout tables that follow, the following variations may be applied:
Note:
The Summit T3‐16 analyzer provides the flexibility to reorder lanes regardless of the
order in which they are physically connected (lane swizzling).
18
PCIe 3.0 Mid‐Bus Probe Installation and Usage Guide
Inner eye width = 82 ps Minimum (see 1 in the following figure)
Inner eye height = 52 mVpp Minimum (see 2 in the following figure)
Maximum signal amplitude 1500 mVpp Maximum (see 3 in the following figure)
The designation of upstream and downstream may be reversed as long as it is
reversed for every lane (all upstream connections on the left and all downstream
on the right may be swapped).
Lane ordering may be reversed if done as a whole such that probe lanes 0, 1, 2,
3, 4, 5, 6, 7 connect to physical lanes 7, 6, 5, 4, 3, 2, 1, 0.
Each differential signal pair may have the D+ and D‐ assignment reversed.
Probed Signal Electrical Requirements
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