Table of Contents
Advertisement
3
VPC3+ PROFIBUS Board
3.4.2 SPI Mode Configuration ( S1 )
If the SPI interface mode is selected the clock polarity and clock phase of
the SPI transmission can be configured with bits 5 and 6 of DIP-switch S1.
These settings need to comply with the corresponding configuration of the
SPI master.
In other interface modes these bits do not have any relevance.
Bit
5
6
Figure 3-10: Configuration of SPI Transmission
3.4.3 VPC3+ Clock Divider Configuration ( S1 )
Bit 8 of DIP-switch S1 configures the clock divider integrated in the VPC3+.
Depending on the level at pin DIVIDER the input clock CLK will be divided
by 2 or 4 and output at pin CLKOUT2/4:
Bit
8
Figure 3-11: Configuration of VPC3+ Clock Divider
28
State
Signal name
OFF
SPI_CPOL
ON
OFF
SPI_CPHA
ON
Signal name
State
DIVIDER
Revision 1.00
Description
SPI Clock Polarity is '0'
SPI Clock Polarity is '1'
SPI Clock Phase is '0'
SPI Clock Phase is '1'
Description
OFF
0: CLK divided by 4 (CLKOUT2/4: 12 MHz)
ON
1: CLK divided by 2 (CLKOUT2/4: 24 MHz)
Copyright © profichip GmbH 2009
VPC3+S Evaluation Kit
Advertisement
Table of Contents
