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hilscher netRAPID 90 Design Manual

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Design guide
netRAPID 90
Chip Carrier
Hilscher Gesellschaft für Systemautomation mbH
www.hilscher.com
DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public

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  • Page 1 Design guide netRAPID 90 Chip Carrier Hilscher Gesellschaft für Systemautomation mbH www.hilscher.com DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 2: Table Of Contents

    Requirements for design-in................ 12 2.3.3 Connections overview.................. 13 2.3.4 Benefits of netRAPID90 ..................  14 netRAPID 90 variants..................... 15 2.4.1 Overview netRAPID 90 products .............. 15 2.4.2 Memory options .................... 15 2.4.3 Preloaded vs. open platform ................ 16 Solutions for typical applications .................. 17 2.5.1 Companion solution providing a fixed layout ..........
  • Page 3 SYS LED (P300) .....................  79 7.4.2 COM0 LED (P400).................. 80 7.4.3 COM1 LED (P401).................. 80 7.4.4 User LEDs (P500-P503) .................  81 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 4 10 Bill of material ........................ 97 10.1 Overview ........................ 97 10.2 NRPEB H90-RE ...................... 97 11 Appendix.......................... 100 11.1 Legal notes........................ 100 Contacts.......................... 108 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 5: Introduction

    Introduction 5/108 1 Introduction About this document This design guide describes the mechanical and electrical interfaces of netRAPID 90. This document also includes the description of the netRAPID 90 Evaluation Board. List of revisions Date Name Chapter Revision 2019-09-11 RGö/ Created.

  • Page 6: Product Concept And Overview

    (application is executed on · the APP CPU of netX 90) On top netRAPID 90 is the perfect way for rapid prototyping of netX90 and one can easily migrate to a real chip-design after a ramp-up phase. 2.1.1...

  • Page 7: Stand-Alone Solution: Programming Platform Like A Netx Chip

    7/108 2.1.2 Stand-alone solution: Programming platform like a netX chip You can use netRAPID 90 in a stand-alone solution without any host. This use case can be considered as nearly identical to the direct use of a netX 90 chip.

  • Page 8: One Design With Different Memory Options

    2.1.3 One design with different memory options A netRAPID 90 is a scalable platform for various use cases, from pure communication interface up to intelligent field device with integration customer application. It is a single hardware design, which comes in different memory options and subsequent different software functionality: ·...

  • Page 9: Overview Netx90 Base Technology

    Internal structure of the netX90 The following figure shows a block diagram of the netX 90. Figure 1: Block diagram of netX90 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 10: Security Concept Netx90 And Netx90 Based Products

    There is no TPM chip necessary. 2.2.4 Software concept netX90 and netX90 based products Common software application interface Figure 2: Common software application interface netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 11: Table 3: Com Channels For Cyclic And Acyclic Data To The Application

    Uses same software application interface whether: · – from external host (→ Companion Solution) – or internal host application (→ Stand-alone Solution) netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 12: Overview Netrapid 90

    Product concept and overview 12/108 Overview netRAPID 90 2.3.1 Features netRAPID 90 netRAPID 90 offers the following features: Ultra-compact design for small field devices · · All major Real-Time Ethernet, Fieldbus and IIoT standards are supported. · Built-in security for secure connectivity to field and cloud ·...

  • Page 13: Connections Overview

    Product concept and overview 13/108 2.3.3 Connections overview The figure below illustrates all connections of the netRAPID 90 chip carrier regardless of the mode they are intended for (companion solution or stand- alone solution). Figure 3: Block diagram of NRP H90-RE and its interfaces netRAPID 90 | Design guide ©...

  • Page 14: Benefits Of Netrapid90

    Ready-to-use netX 90 design The fully tested netX 90 design ensures a fast time to market without · development risk EOL and part obsolescence handling by Hilscher · RTE or FB interface in one design · Reduced design and production costs ·...

  • Page 15: Netrapid 90 Variants

    Product concept and overview 15/108 netRAPID 90 variants 2.4.1 Overview netRAPID 90 products Overview The following table lists all variants of netRAPID 90, the corresponding evaluation board and the appropriate firmware: Products Description Part number NRPEB H90-RE Evaluation board equipped with soldered-in NRP H90-RE\F8D8 7600.320...

  • Page 16: Preloaded Vs. Open Platform

    2520 pieces \F0D0 memory Table 6: Packaging units netRAPID 90 (bare metal) For the bare netRAPID 90, the same loadable firmware is available as for netX90. A netX license and support agreement as well as a purchase of an appropriate protocol stack is required! netRAPID 90 | Design guide ©...

  • Page 17: Solutions For Typical Applications

    Product concept and overview 17/108 Solutions for typical applications 2.5.1 Companion solution providing a fixed layout As companion solution, the netRAPID 90 has a fixed pin assignment and offers the following features: · Real-time Ethernet or Fieldbus interface · netRAPID 90 serves for communication only, its application CPU is not used in this case ·...

  • Page 18: Mechanics

    Mechanics 18/108 3 Mechanics Dimension netRAPID 90 chip carrier has the following dimensions: · Length 31.75 mm (corresponding to 1250 mil) · Width 15.00 mm (corresponding to 590 mil) · Height 4 mm. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 19: Design Guidelines For The Host System

    Mechanics 19/108 Design guidelines for the host system 3.2.1 Footprint The layout for the footprint of the netRAPID 90 on the host system requires the following dimensions. 15 mm 1.27 mm 3.062 mm 2.4 mm 1 mm R 0.5 mm Thermal pad 9.5 mm...

  • Page 20: Thermal Behavior And Thermal Pad

    90 to avoid heat dissipation of other component than netRAPID 90. The thermal pad of the netRAPID device must have GND potential. The figure shows position and size of the thermal pad for netRAPID 90. 3.2.3 VIAs and signal fan out underneath the netRAPID device Make sure that no vias and no wires are on the PCB of the host system underneath the netRAPID device.

  • Page 21: Tempering, Storage And Soldering

    To avoid this, the netRAPID chip carriers have to be tempered 24 h at 80°C. Hilscher tempers netRAPID devices before they are shipped. After tempered, netRAPID devices are shipped welded within a tray.

  • Page 22: Matrix Label

    The figure shows part number 7690.102 denoting NRP H90-RE\F8D8, hardware revision 1 and serial number 00200. Part number Hardware Revision Serial number Table 7: Matrix label netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 23: Electrical Aspects Common For Both Solutions

    Location of pins The following figure shows the position of contacts 1, 9, 28 and 36. Pin numbering has been done counter-clockwise. Figure 6: netRAPID 90 - Pin numbering and orientation This figure applies for both NRP H90-RE and NRP H90-RE\F8D8. General signals 4.2.1...

  • Page 24: Reset Signals

    RST_IN has a static low level. To reset the netRAPID 90, the RST_IN signal must be low (2.8 V ± 0.07 V or less) for more than approx. 10 µs. Afterwards, the netRAPID 90 starts the initialization and program execution.

  • Page 25: Boot Signal And Boot Options

    If this does not succeed, the ROM code tries to start a maintenance firmware in alternative boot mode. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 26: Figure 9: Alternative Boot Mode

    Guide (Doc-ID DOC180501DG04EN), p.14, section „Booting and SYS LED“ and netX90 Technical Data Reference Guide (Doc-ID DOC160609TRG03EN), p.59, section „Booting and SYS LED“ netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 27: Real-Time Ethernet Interface

    Note: For more information see section „Real-time Ethernet (RTE) interface“ in the netX 90 Design-In Guide (ref. [2]). netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 28: Design Recommendations

    LED over an appropriate current resistor. Table 8: Ethernet Interface of NRP H90-RE - Assignment of pins and signals 4.3.2 Design recommendations The Ethernet interface for the netRAPID 90 module can be designed as follows: netRAPID 90 | Design guide © Hilscher 2019...

  • Page 29: Figure 10: Proposal For The Design Of The Real-Time Ethernet Interface For The Netrapid 90

    Electrical aspects common for both solutions 29/108 Figure 10: Proposal for the design of the Real-Time Ethernet interface for the netRAPID 90 module (both Ethernet channels displayed) netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 30 For more information on the Real-time Ethernet SYNC-Signals, see Meaning of the SYNC signals for various real-time Ethernet protocols for netX 90. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 31: Diagnostic Interfaces

    The following figure shows in general how to implement a UART interface using the MAX3232 circuit. It contains an excerpt of the schematics of the evaluation board NRPEB H90-RE and shows a more detailed example of a suitable UART interface for netRAPID 90: Figure 11: UART DSub netRAPID 90 | Design guide ©...

  • Page 32: Jtag Debugging Interface

    The netX 90 has a separate debugging interface based on the JTAG standard. However, this debugging interface is not intended to be used by the module user. It is only used in two special cases: during the production of the netRAPID 90 module · ·...

  • Page 33: Led Signals

    Use two red/green LEDs, which cover all Real-Time Ethernet protocols. For details about the circuit for the host system, see Figure 18 on page 54 (NRPEB H90-RE). netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 34: System Led (Sys Led)

    These signals are also used for activation of the alternative boot mode and the console mode, see respective sections of this manual. Figure 12: Console mode netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 35: Leds Com0 And Com1

    They indicate the link (green) and activity status (yellow) of the Ethernet channels 0 and 1. Figure 15: Proposed schematics for controlling LED LINK/ACTIVITY0 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 36: Figure 16: Proposed Schematics For Controlling Led Link/Activity1

    Electrical aspects common for both solutions 36/108 Figure 16: Proposed schematics for controlling LED LINK/ACTIVITY1 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 37: Electrical Aspects For The Companion Solution

    (deact) Unused, leave open ADC1_IN1 MMIO6 / pd (deact) Unused, leave open ADC1_IN0 MMIO5 / pd (deact) Unused, leave open ADC0_IN1 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 38 Ethernet Channel 0: Ethernet PHY, transmit output negative PHY0_RXP PHY0_RXP Ethernet Channel 0: Ethernet PHY, receive input positive netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 39: Table 12: Pin Assignment For The Companion Solution

    = deactivated neither pull-up nor pull-down resistor deact “deactivation required” for analog signals Table 13: Symbols for pull-up/down netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 40: Block Diagram For The Companion Solution

    Electrical aspects for the companion solution 40/108 Block diagram for the companion solution The following block diagram explains how to apply the netRAPID 90 within the companion solution: Figure 17: netRAPID - Companion solution netRAPID 90 | Design guide © Hilscher 2019...

  • Page 41: Host Interface

    Serial dual-port memory mode 5.3.1.1 General description The netRAPID 90 offers a serial dual-port memory interface, which is a SPI Slave interface. The Serial Peripheral Interface (SPI) is a versatile bus system for the synchronous serial communication of digital electronic circuits allowing versatile applications.

  • Page 42: Design Recommendation

    If other settings differing from the default settings are required, then these have to be specified using the tool netX Studio CDT that is included on the DVD delivered together with the netRAPID 90. 5.3.1.4 Host interface signal buffers...

  • Page 43: Fieldbus Interface

    Fieldbus interface 5.4.1 PROFIBUS-DP The following figure shows a proposal for implementing a PROFIBUS-DP interface ae the additional Fieldbus interface of the netRAPID 90: Figure 19: PROFIBUS-DP interface of netRAPID 90 5.4.2 DeviceNet The following figure shows a proposal for implementing a DeviceNet interface at the additional Fieldbus interface of the netRAPID 90: Figure 20: DeviceNet interface of netRAPID 90...

  • Page 44: Sync0/1 Signals

    The following table shows the meaning of the SYNC signals for the real- time Ethernet protocols currently offering SYNC signal support. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 45 Sercos Slave CON_CLK DIV_CLK Configurable Table 16: Meaning of the SYNC signals for various real-time Ethernet protocols for netX 90 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 46: Electrical Aspects For The Stand-Alone Solution

    SPI1: Master In / Slave Out signal or Status LED HIF_D13 MMIO13, Multiplex matrix I/O signal SQI1_APP_CLK or SQI1/SPI1: Clock signal or MLED9 Status LED netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 47 Bidirectional/Serial/Synchronous 0 data output, ENDAT0_OUT or Encoder Data 0 data output IO_LINK0_OUT IO-Link 0 output Leave open if unused netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 48 Ethernet Channel 0: Ethernet PHY, transmit output positive PHY0_TXN PHY0_TXN Ethernet Channel 0: Ethernet PHY, transmit output negative netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 49: Table 13: Symbols For Pull-Up/Down

    = deactivated neither pull-up nor pull-down resistor deact “deactivation required” for analog signals Table 18: Symbols for pull-up/down netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 50: Block Diagram For The Stand-Alone Solution

    Electrical aspects for the stand-alone solution 50/108 Block diagram for the stand-alone solution The following block diagram explains how to apply the netRAPID 90 within the stand-alone solution: Figure 22: netRAPID – Stand-alone solution netRAPID 90 | Design guide © Hilscher 2019...

  • Page 51: General Signals

    For the configuration of the specific pinout, use the hardware configuration tool with integrated GUI within netX Studio CDT. The following requirements apply for the MMIO signals of the netRAPID 90. The signals MMIO00, MMIO01, MMIO02 and MMIO03 may serve as ·...

  • Page 52: Adcs

    In order to serve these signals, you have to provide an application running on the APP CPU of the netX 90 processor. ADCs The netRAPID 90 allows access to three of the four independently operating 12-bit ADC units of the netX 90, which are denominated as ADC0, ADC1 and ADC3.
  • Page 53 Serial kΩ resistance ADC_WARMUP Warm-up ADC_ENA μs time BLE 0 →1 ADC_REF Reference T=27 °C 2.55 2.65 voltage netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 54 VSS_REF Note: For more information, see section 3.14 „Analog to digital converter“ of netX 90 Design-in Guide, p.37. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 55: Evaluation Board

    Extension interface (X304) [} page 68] S600 Multiple switch (for JTAG, UART, SPM and user- Extension switches defined LEDs) (S600) [} page 59] netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 56: Table 21: Positions On Nrpeb H90-Re

    NRP H90-RE (soldered-in) (22) X308 UART interface (DSub, 9-pin) UART interface (X308) [} page 72] Table 21: Positions on NRPEB H90-RE netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 57: Operating Elements Of The Evaluation Board

    When S300-B is switched on, the RDY# signal (pin #38) of the netX 90 is connected to GND via a 1kΩ resistor, see figure below: Figure 26: Console mode netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 58 Evaluation Board 58/108 The console mode can be used for flashing firmware via the UART interface. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 59: Figure 27: Reset Logic

    Switch S600-B allows switching between different modes of using the UART interface, which are explained in the following table: netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 60 User LEDs disabled ADCs disabled User LEDs enabled Table 25: Switch S600-D – Switching between ADCs and User LEDs netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 61: Figure 28: Adc

    Evaluation Board 61/108 Figure 28: ADC Figure 29: User defined LEDs netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 62: Figure 30: User Defined Inputs

    These values affect the signals MMIO00, MMIO01, MMIO02 and MMIO03. Figure 30: User defined inputs netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 63: Jumper Field X501

    If the pins of X501 are bridged, then ADC presets will be used, otherwise the ADCs can be supplied with external signals. Figure 31: ADC netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 64: Interfaces

    NXHX fieldbus modules XM0_IO0 XM0_TX XM0_RX +3V3 XM0_IO1 X300 NXHX-AIF Male Connector Figure 32: Fieldbus interface for external NXHX FB-Module netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 65: Jtag Interface (X301)

    Never connect pin 16 of JTAG interface X301 to signal TRST. Doing so may destroy both your evaluation board and your debugging hardware. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 66: Extension Interface (X302)

    Signal Signal MMIO01 MMIO00 MMIO03 MMIO02 +3V3 MMIO05 MMIO04 MMIO07 MMIO06 Table 29: Connectors Extension interface (X302) Figure 33: NXHX-ENC-Module netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 67: Com Io (X303)

    GPIO/ COM_IO signals of the netX 90 (currently not supported). Pin 28 of the netRAPID 90 corresponds to COM IO0 and pin 29 to COM IO1.. The connector of this interface of the NRPEB H90-RE is a male single-row pin header with 4 pins.

  • Page 68: Extension Interface (X304)

    Extension interface (X304) The extension interface (X304) of the NRPEB H90-RE is used only for connecting to external modules of type NXHX-RS232 (Hilscher part number 7923.100).. At a given time, only one of the interfaces X304 (Pin header) and X308 (DSub connector) can be used.

  • Page 69: Sync0/1 Signals (X305)

    Meaning of the SYNC signals for various real-time Ethernet protocols for netX 90. Figure 36: SYNC connectors netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 70: Sync0/1 Signals (X306)

    Meaning of the SYNC signals for various real-time Ethernet protocols for netX 90. Figure 37: SYNC connectors netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 71: Reset Out Signal (X307)

    For more information, see the netX90 Design-In Guide (Doc-ID DOC180501DG04EN), p.12 „Power-on reset and reset in“. Figure 38: Reset Logic netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 72: Uart Interface (X308)

    UART over X304 is deactivated and UART over DSub is active. See section UART Switch (S600-B). Figure 39: UART DSub netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 73: Sqi Interface (X309)

    +3V3 10/37 n.c. 9/36 SQI0_APP_CLK SQI0_APP_CS0# SQI0_APP_MOSI SQI0_APP_MISO SQI0_APP_SIO2 SQI0_APP_SIO3 Table 35: SQI interface (X309) Figure 40: SQI interface netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 74: Ethernet Interface (X400)

    Connected and terminated to PE via RC combination (Bob Smith Termination) Term 2 RJ45 socket, female Table 36: Ethernet RJ45 pin assignment netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 75: Adc Reference Voltage Vref-Adc (X500)

    This figure also shows the signal directions. At least the signals SPM_CLK, SPM_CS#, SPM_MOSI und SPM_MISO and GND must be connected. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 76: Usb Interface For Spm - Nrpeb H90-Re (X700)

    USB" as listed in Extension switches (S600) [} page 59]Table 24. The USB interface X700 requires switch S600-A to be open. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 77: Power Connector (X800)

    Cable length 1,8 m Connector With barrel connector, sizes in mm Table 40: Technical data - Power supply NXAC-POWER netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 78: Leds

    Ethernet channel 1 yellow Meaning depends on applied Real-Time Ethernet protocol. Table 41: LEDs of evaluation board NRPEB H90-RE netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 79: Sys Led (P300)

    SYS LED (P300) The SYS LED is a Duo-LED with the colors yellow and green. It provides information on the current system status of the netRAPID 90. A solid green SYS LED indicates that the firmware of the netRAPID H90 is operational (Pin #39 RUN#).

  • Page 80: Com0 Led (P400)

    Duo-LED COM1. In order to separate both components, the following circuitry is used: Figure 45: COM1 LED netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 81: User Leds (P500-P503)

    LEDs, switch S600-D must be closed enabling the user LEDs and simultaneously disabling the ADCs. Figure 46: User defined LEDs netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 82: Link/Activity0/1 (X400-C/D)

    Duo-LED X400-D. In order to separate both components, the following circuitry is used: Figure 48: LINK/ACTIVITY1 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 83: Accessories

    Part number PROFIBUS-DP NXHX-DP 7923.410 CANopen NXHX-CO 7923.500 DeviceNet NXHX-DN 7923.510 CC-Link NXHX-CC 7923.740 Table 43: Fieldbus interface modules (NXHX-FB) netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 84: Profinet-Dp Interface Module Nxhx-Dp

    1, 2, 4, 6, 7, 9 n.c. 9 pin, D-Sub, female Table 45: PROFIBUS-DP pin assignment (RS-485) netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 85: Canopen Interface Module Nxhx-Co

    CAN High signal DN V+ +24 V DeviceNet COMBICON socket, power supply 5 pin, female Table 49: DeviceNet pin assignment netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 86: Cc-Link Interface Module Nxhx-Cc

    Internally connected via 3.3 nF to DG. Table 51: CC-Link pin assignment Currently, no firmware supporting CC-Link is available for the netRAPID 90. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 87: Nxhx Rs232 Interface Modules

    Table 53: RS232 interface modules (NXHX-RS) Note: Each RS232 module requires the appropriate RS232-specific communication firmware on the netX. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 88: Rs232 Interface Module

    Request to send Clear to send 1, 6, 9 n. c. 9 pin, D-Sub, male Table 55: RS232 pin assignment netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 89: Schematics

    CPU, which is a standard PC, can be connected to the serial host interface connector (X600). NRPEB H90-RE - Front view Figure 53: NRP H90-RE - Front view netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 90: Nrpeb H90-Re Ethernet

    Schematics 90/108 NRPEB H90-RE ETHERNET Figure 54: NRPEB H90-RE ETHERNET netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 91: Nrpeb H90-Re Ftdi

    Schematics 91/108 NRPEB H90-RE FTDI Figure 55: NRPEB H90-RE FTDI netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 92: Nrpeb H90-Re Io Adc

    Schematics 92/108 NRPEB H90-RE IO ADC Figure 56: NRPEB H90-RE IO ADC netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 93: Nrpeb H90-Re Netrapid

    Schematics 93/108 NRPEB H90-RE NETRAPID Figure 57: NRPEB H90-RE NETRAPID netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 94: Nrpeb H90-Re Power_Supply

    Schematics 94/108 NRPEB H90-RE POWER_SUPPLY Figure 58: NRPEB H90-RE POWER_SUPPLY netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 95: Nrpeb H90-Re Switching Matrix

    Schematics 95/108 NRPEB H90-RE SWITCHING MATRIX Figure 59: NRPEB H90-RE SWITCHING MATRIX netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 96: Nrpeb H90-Re System

    Schematics 96/108 NRPEB H90-RE SYSTEM Figure 60: NRPEB H90-RE SYSTEM netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 97: 10 Bill Of Material

    Dual High Speed USB to FT2232HQ Future Multipurpose UART/FIFO IC Technology Devices Int. K300 RS232 Transceiver MAX3232EEUP Maxim netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 98 Resistor SMD 0402 RC0402 Samsung 3.3kΩ±1%,-55…155°C, 63 mW R200 R506 R512 Resistor SMD 0402 RC0402 Yageo R709 4.7kΩ,-55…155°C, 63 mW netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 99: Table 56: Bill Of Material For Evaluation Board Nrpeb H90-Re

    Suyin X306 Pin header SMT, 3 pins 53398-0371 Molex Table 56: Bill of material for evaluation board NRPEB H90-RE netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 100: 11 Appendix

    The manual delivered with the product shall apply. Under no circumstances shall Hilscher Gesellschaft für Systemautomation mbH be liable for direct, indirect, ancillary or subsequent damage, or for any loss of income, which may arise after use of the information contained herein.
  • Page 101 Appendix 101/108 Liability disclaimer The hardware and/or software was created and tested by Hilscher Gesellschaft für Systemautomation mbH with utmost care and is made available as is. No warranty can be assumed for the performance or flawlessness of the hardware and/or software under all application conditions and scenarios and the work results achieved by the user when using the hardware and/or software.
  • Page 102 The customer hereby expressly acknowledges that this document contains trade secrets, information protected by copyright and other patent and ownership privileges as well as any related rights of Hilscher Gesellschaft für Systemautomation mbH. The customer agrees to treat as confidential all of the information made available to customer by Hilscher Gesellschaft für...
  • Page 103 Terms and conditions Please read the notes about additional legal aspects on our netIOT web site under http://www.netiot.com/netiot/netiot-edge/terms-and- conditions/. netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 104 Footprint of netRAPID 90 ..................19 Figure 5: Thermal profile for reflow soldering of NRP H90-RE..........22 Figure 6: netRAPID 90 - Pin numbering and orientation ............. 23 Figure 7: Reset Logic IN ...................... 24 Figure 8: Reset Logic OUT ....................25 Figure 9: Alternative boot mode...................
  • Page 105 NRPEB H90-RE POWER_SUPPLY..............94 Figure 59: NRPEB H90-RE SWITCHING MATRIX ............... 95 Figure 60: NRPEB H90-RE SYSTEM..................96 netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...
  • Page 106 COM channels for cyclic and acyclic data to the application ........Table 4: Product overview netRAPID 90 ................Table 5: Packaging units netRAPID 90 preloaded with communication protocol ....Table 6: Packaging units netRAPID 90 (bare metal) ............Table 7: Matrix label ......................
  • Page 107 NXHX-RS technical data ..................Table 55: RS232 pin assignment.................... Table 56: Bill of material for evaluation board NRPEB H90-RE ..........netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

  • Page 108: Contacts

    Phone: +1 630-505-5301 E-mail: info@hilscher.it E-mail: info@hilscher.us Support Support Phone: +39 02 25007068 Phone: +1 630-505-5301 E-mail: it.support@hilscher.com E-mail: us.support@hilscher.com netRAPID 90 | Design guide © Hilscher 2019 DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public...

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