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5
CPUCLK
0.5" MAX
RS
MCHCLK
L1
CPUCLK#
RS
L1
MCHCLK#
D
MCH_66
0"~ 0.5 "
ICH_66
L1
AGP_66
ICH_PCLK
FWH_PCLK
0"~ 0.5 "
SIO_PCLK
L1
C
ISAPCLK
PCICLK[4..0]
0"~ 0.5 "
ICH_14
L1
OSC
ICH_48
0"~ 0.5 "
SIO_48
L1
B
CK 408
RN
0.5" TO 6.5"
A
LAN_PCLK
RST
A
RXD[2..0]
ICH2
TXD[2..0]
AS SHORT AS POSSIBLE
5
4
0"~ 0.2"
2"~ 9"
L2
L4
L2
L4
0"~ 0.2"
L3
L3
GND
4"~ 8.5"
RS
L2
4"~ 8.5"
RS
L2
4"~ 8.5"
RS
L2
3"~12"
RS
L2
2.5" TO 9"- A
CNR
4
3
DEVICE
L1+L2
* Line Width : 7.0 mil
CPU
X
* Differential pair spacing : 7.0mil
MCH
X
* Spacing to other traces : 28 mil
ITP
X
* BCLK0/BCLK1 LENGTH MATCH +/- 10 mil
DEVICE
L1+L2
* Line Width : 5.0 mil
MCH
X
* Spacing to other traces : 20 mil
ICH
X +/- 100 mils
AGP
X- 4"
DEVICE
L1+L2
* Line Width : 5.0 mil
ICH
X
* Spacing to other traces : 20 mil
FWH
X
* L1/L2 TRACE SAME AS MCH_66 TRACE LENGTH
SIO
X
PCI
X-2.5"
DEVICE
L1+L2
* Line Width : 5.0 mil
ICH
Y
* Spacing to other traces : 10 mil
ISA BRIDGE
Y
DEVICE
L1+L2
* Line Width : 5.0 mil
ICH
* Spacing to other traces : 20 mil
SIO
3
2
1
* Line Width : 7.0 mil
* Differential signls space : 14mils
* Differential signls length mismatch +/- 7mil
Title
Micro-Star
MS-6507
Document Number
CK-408 and LAN Design Guide
Last Revision Date:
Monday, September 24, 2001
Sheet
2
1
D
C
B
A
Rev
1.0
32
of
36
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