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Trigger Input
Synchronization
Trigger Output
The PXIe-6674 board supports synchronous routing to either the rising or falling edge of the
synchronization clock. In addition, the polarity of the destination signal can be inverted, which
is useful when handling active-low digital signals. Synchronous routing can be useful for
eliminating skew when sending triggers to several destinations. For example, when sending
triggers using the PXI Trigger lines, the trigger arrives at each slot at a slightly different time.
However, if the trigger is sent and received synchronously using a low-skew synchronization
clock (for example, PXI_CLK10), all receiving devices can act on the trigger at the same time,
as shown in
Figure 9.
Figure 9. Synchronous Routing to Multiple Destinations
Trigger Synchronously Received
Synchronous routing requires the input to be stable at a logic low or logic high state with a
window of time around the clock edge. This window of time around the clock edge is defined
by the setup time (t
setup
Figure 8. Synchronous Routing Operation
Clock
on page 23:
PXI_CLK10
Trigger Out@Source
Trigger@Destination 1
Trigger@Destination 2
@Destinations 1 and 2
A: Propagation delay from source to destination 1.
B: Propagation delay from source to destination 2.
) and hold time (t
hold
Setup
Hold
Time
Time
t
t
setup
hold
Clock to Output
Time, t
A
B
). If the input signal changes within this window of
PXIe-6674 User Manual | © National Instruments | 23
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