National Instruments PXIe-6674 User Manual page 15

Figure 4. on page 15 and
PXIe-6674. The remainder of this chapter details the capabilities and constraints of the routing
architecture.
Figure 4. High-Level Schematic of PXIe-6674 Signal Routing Architecture
Selection
PFI_LVDS 0
Circuitry
Selection
PFI_LVDS 1
Circuitry
Selection
PFI_LVDS 2
Circuitry
Selection
PFI 0
Circuitry
Selection
PFI 1
Circuitry
Selection
PFI 2
Circuitry
Selection
PFI 3
Circuitry
Selection
PFI 4
Circuitry
Selection
PFI 5
Circuitry
CLKIN
OCXO
Clock Generation
PXIe-CLK100
PXI_CLK10
CLKIN
OCXO
Clock Generation
PXIe-CLK100
PXI_CLK10
Figure 5. on page 16 provides a more detailed view of the selection circuitry referenced in
Figure 4. on page 15.
Figure 5. on page 16 summarize the routing features of the
*
PXI_STAR<0..16>, PXI_TRIG<0..7>,
PFI<0..5>, PFI_LVDS<0..2>,
PXIe_DSTARC<0..16>, Steady
Logic, and Software Trigger are
routed to SOURCE of each Selection
Circuitry block.
3
SYNCHRONIZATION
CLOCKS for PFI<0..5>
and PFI_LVDS<0..2>
N
÷2
M
÷2
N
÷2
M
÷2
53
*
SOURCE
3
SYNCHRONIZATION CLOCKS
for PXI_STAR<0..16>, PXI_TRIG<0..7>,
and PXIe-DSTARB<0..16>
PXIe-6674 User Manual | © National Instruments | 15
Selection
PXIe_DSTARB 0
Circuitry
Selection
PXIe_DSTARB 1
Circuitry
Selection
PXIe_DSTARB 16
Circuitry
Selection
PXI_STAR 0
Circuitry
Selection
PXI_STAR 1
Circuitry
Selection
PXI_STAR 16
Circuitry
Selection
PXI_TRIG 0
Circuitry
Selection
PXI_TRIG 1
Circuitry
Selection
PXI_TRIG 7
Circuitry