National Instruments sbRIO-9651 Design Manual
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National Instruments sbRIO-9651 Design Manual

System on module, carrier board
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NI sbRIO-9651
System on Module
Carrier Board Design Guide
NI sbRIO-9651 System on Module Carrier Board Design Guide
March 2017
376960C-01

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Summary of Contents for National Instruments sbRIO-9651

  • Page 1 NI sbRIO-9651 System on Module Carrier Board Design Guide NI sbRIO-9651 System on Module Carrier Board Design Guide March 2017 376960C-01...
  • Page 2 11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 683 0100 NI Services For further support information, refer to the appendix. To comment on National Instruments documentation, refer to the National Instruments website at ni.com/info enter the Info Code feedback...
  • Page 3 National Instruments Corporation. National Instruments respects the intellectual property of others, and we ask our users to do the same. NI software is protected by copyright and other intellectual property laws. Where NI software may be used to reproduce software or other materials belonging to others, you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction.
  • Page 4 ™ The ExpressCard word mark and logos are owned by PCMCIA and any use of such marks by National Instruments is under license. The mark LabWindows is used under a license from Microsoft Corporation. Windows is a registered trademark of Microsoft Corporation in the United States and other countries.

  • Page 5: Table Of Contents

    FPGA Config ........................1-21 FPGA Config Signal Definitions................1-21 FPGA Config Implementation on the Reference Carrier Board ......1-21 Temp Alert........................1-22 Temp Alert Signal Definitions ................. 1-22 Temp Alert Implementation on the Reference Carrier Board ........1-22 © National Instruments | v...
  • Page 6 Contents Chapter 2 User-Defined FPGA Signals Secondary Ethernet (GBE1) ..................... 2-1 GBE1 Signal Definitions on the Reference Carrier Board ........2-2 GBE1 Reference Schematic..................2-4 GBE1 Routing Considerations.................. 2-8 Additional RS-232 (Serial2, Serial3, Serial4) ..............2-9 Serial2 Signal Definitions on the Reference Carrier Board........2-9 Serial2 Reference Schematic ..................
  • Page 7 NI sbRIO-9651 System on Module Carrier Board Design Guide Appendix A Reference Carrier Board Specifications and User Guide Parts Locator Diagram and Block Diagram ..............A-1 Specifications........................A-1 Ethernet........................A-2 Serial......................... A-2 CAN.......................... A-2 SD Card ........................A-2 USB .......................... A-2 Pmod.........................

  • Page 8: About This Document

    Module OEM Device Specifications for dimensions, pinout information, functional specifications, and electrical specifications for the sbRIO-9651 SOM. Terminology Table 1 defines terms used in this document to describe sbRIO-9651 SOM concepts and technology. Table 1. sbRIO-9651 SOM Terminology in This Document...

  • Page 9: Schematic Conventions

    About This Document Table 1. sbRIO-9651 SOM Terminology in This Document (Continued) Term Definition Reference Schematic and Signal Naming LVTTL In compliance with the Low-Voltage Transistor-Transistor Logic (LVTTL) specification. LVCMOS In compliance with the Low-Voltage Complementary Metal Oxide Semiconductor (LVCMOS) specification.

  • Page 10: Additional Documentation Resources

    NI sbRIO-9651 System on Module Carrier Board Design Guide Table 2. Schematic Conventions in This Document (Continued) Symbol Description On-page symbol that represents the signal being received. Power supply rail. Analog ground. Digital ground. Chassis ground. SPARE Refers to an unpopulated reference designator.
  • Page 11 About This Document What Would You Like to Resources Availability Learn More About? NI sbRIO-9651 NI sbRIO-9651 System on Module System on Module OEM Device OEM Device Specifications NI sbRIO-9651 NI sbRIO-9651 System on Module System on Module Development Kit...

  • Page 12: Fixed Behavior Signals

    Fixed Behavior Signals A subset of pins on the J1 connector on the sbRIO-9651 SOM are dedicated to implementing the following specific I/O functionality: • Primary Ethernet (GBE0) • USB Host/Device (USB0) • USB Host (USB1) • UART/Console Out (Serial1) •...

  • Page 13: Gbe0 Signal Definitions

    GBE0_MDI0_P Defined by Pre-magnetic GBE0_MDI0_N Ethernet Gigabit Ethernet GBE0_MDI1_P data pairs. GBE0_MDI1_N specification. GBE0_MDI2_P GBE0_MDI2_N GBE0_MDI3_P GBE0_MDI3_N GBE0_SPEED_LEDg LVTTL Speed LED GBE0_SPEED_LEDy signals. GBE0_ACT_LEDg LVTTL Activity/link LED signal. I/O direction is with respect to the sbRIO-9651 SOM. 1-2 | ni.com...

  • Page 14: Gbe0 Implementation On The Reference Carrier Board

    NI sbRIO-9651 System on Module Carrier Board Design Guide GBE0 Implementation on the Reference Carrier Board Figure 1-1 shows a schematic design for the GBE0 implementation on the reference carrier board. Figure 1-1. GBE0 Reference Schematic GBE0_MDIO_P MDIA_P GBE0_MDIO_N MDIA_N~...

  • Page 15: Gigabit Ethernet Magnetic Requirements

    Fixed Behavior Signals Gigabit Ethernet Magnetic Requirements The Ethernet PHY on the sbRIO-9651 SOM uses voltage-mode drivers for the MDI pairs, which greatly reduces the power that the magnetics consume and eliminates the need for a sensitive center tap power supply.

  • Page 16: Usb (Usb0, Usb1)

    Ethernet compliance was tested. USB (USB0, USB1) The sbRIO-9651 SOM provides two USB 2.0-compliant ports for use on a carrier board: USB Host/Device port (USB0) and USB Host port (USB1). Your carrier board design must provide the 5 V USB_VBUS power to...

  • Page 17: Usb0 Device Implementation On The Reference Carrier Board

    Chapter 1 Fixed Behavior Signals Configuring the USB0 Mode You can configure the USB0 interface to be a USB Host port or a USB Device port, as shown in Table 1-6. This mode is set when the system boots and does not change dynamically. The reference carrier board uses the USB0 interface for a USB Device port.

  • Page 18: Usb1 Host Signal Definitions

    USB connector. NI recommends that you use a 1 kΩ resistor. USB1 Host Signal Definitions Table 1-8 describes the USB1 Host port pins and signals on the sbRIO-9651 SOM connector. Table 1-8. USB1 Host Signal Definitions Dedicated...

  • Page 19: Usb1 Host Implementation On The Reference Carrier Board

    Allows USB PHY to sense if VBUS is present on the connector. I/O direction is with respect to the sbRIO-9651 SOM. USB1 Host Implementation on the Reference Carrier Board Figure 1-3 shows a schematic design for the USB1 Host implementation on the reference carrier board.
  • Page 20 VBUS on the USB connector. • This is a low-current, voltage-sense connection. • In layout, you can treat the trace after R92 going to the sbRIO-9651 SOM connector as a data signal. • R92 helps provide some overvoltage protection on USB1_VBUS and should be placed close to the USB connector.

  • Page 21: Supporting Onboard Usb Devices

    Fixed Behavior Signals Supporting Onboard USB Devices When you implement a USB device directly on your carrier board, you can connect the device to a USB Host port from the sbRIO-9651 SOM. For this case, use the following design guidelines: •...

  • Page 22: Serial1 Implementation On The Reference Carrier Board

    NI sbRIO-9651 System on Module Carrier Board Design Guide Table 1-10. Serial1 Signal Definitions Dedicated Signal Name SOM Pin # Direction Standard Description SERIAL1_TX LVTTL Two-wire serial and console out signals for SERIAL1_RX the sbRIO-9651 SOM. I/O direction is with respect to the sbRIO-9651 SOM.

  • Page 23: Adding Flow Control And Modem Control Signals

    CLIP Generator application. SD Card The sbRIO-9651 SOM provides a Secure Digital (SD) Card interface for use on a carrier board. This interface supports SD and SDHC cards. You can implement this interface with standard SD or microSD card connectors. The maximum supported SDHC card capacity is 32 GB.

  • Page 24: Sd Signal Definitions

    NI sbRIO-9651 System on Module Carrier Board Design Guide SD Signal Definitions Table 1-12 describes the SD pins and signals on the sbRIO-9651 SOM connector. Table 1-12. SD Signal Definitions Dedicated Signal Name SOM Pin # Direction I/O Standard Description...

  • Page 25: Sd Implementation On The Reference Carrier Board

    Chapter 1 Fixed Behavior Signals SD Implementation on the Reference Carrier Board Figure 1-5 shows a schematic design for the SD implementation on the reference carrier board. Figure 1-5. SD Reference Schematic +3.3V SD_PWR_EN 4.7 K 0 5% 0.5% 1/16 W 1/16 W +3.3 V SD_OC#...
  • Page 26 Table 1-13. SD Reference Schematic Design Considerations Consideration Notes SD_CLK, • You can route these signals directly from the sbRIO-9651 SOM to the SD connector. SD_CMD, and SD_D0 through • Each of these signals requires series termination near its driver. The...

  • Page 27: Sd Routing Considerations

    The reference carrier board contains a lithium cell battery that maintains the real-time clock (RTC) on the sbRIO-9651 SOM when the sbRIO-9651 SOM is powered off. A slight drain on the battery occurs when power is not applied to the sbRIO-9651 SOM. For information about the VBAT current drain, refer to the VBAT Requirements section of the NI sbRIO-9651 System on Module OEM Device Specifications.

  • Page 28: Vbat Signal Definitions

    Eliminating the Effects of Contact Bounce If you are using the A revision of the sbRIO-9651 SOM, it is important to eliminate the effects of contact bounce when you initially attach the battery. To determine the revision, check the bottom side of the sbRIO-9651 SOM for Note a sticker with the part number 157660x-01L, where x is the revision letter.

  • Page 29: Resets

    Filter the signal using a small capacitor between VBAT and ground. The manufacturer recommends capacitor values between 0.1 nf and 1.0 nf. Resets The sbRIO-9651 SOM provides signals for implementing a reset button on a carrier board and indicating that the sbRIO-9651 SOM is in reset. Reset Signal Definitions Table 1-15 describes the Reset pins and signals on the sbRIO-9651 SOM connector.

  • Page 30: Reset Implementation On The Reference Carrier Board

    C0402 SPARE 720176-01 Refer to the SYS_RST# and CARRIER_RST# sections of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the Reset signals. Reference Schematic Design Considerations Table 1-16 lists design considerations for the schematic shown in Figure 1-7.

  • Page 31: Status Led

    Fixed Behavior Signals Status LED The sbRIO-9651 SOM provides a Status LED signal for use on a carrier board. The Status LED indicates the status of the SOM boot process or Safe Mode and can be used to report software errors.

  • Page 32: Fpga Config

    NI sbRIO-9651 System on Module Carrier Board Design Guide FPGA Config The sbRIO-9651 SOM provides an FPGA Config signal to indicate when the FPGA is configured. FPGA Config Signal Definitions Table 1-18 describes the FPGA Config pins and signals on the sbRIO-9651 SOM connector.

  • Page 33: Temp Alert

    Fixed Behavior Signals Temp Alert The sbRIO-9651 SOM provides a Temp Alert signal to indicate that the onboard CPU/FPGA or Primary System temperature has exceeded the minimum or maximum temperature specifications of the sbRIO-9651 SOM. Refer to the Environmental section of the NI sbRIO-9651 System on Module OEM Device Specifications for the minimum and maximum temperature specifications.

  • Page 34: User-Defined Fpga Signals

    When you create your own CLIP, you must compile your FPGA VI and download it to the flash of the sbRIO-9651 SOM. This ensures that the driver for each enabled peripheral can load properly at boot time. Refer to the Downloading an FPGA VI to the Flash Memory of an FPGA Target topic in the LabVIEW Help (FPGA Module) for more information.

  • Page 35: Gbe1 Signal Definitions On The Reference Carrier Board

    User-Defined FPGA Signals GBE1 Signal Definitions on the Reference Carrier Board Table 2-1 describes the GBE1 pins and signals on the sbRIO-9651 SOM connector used to implement a secondary Ethernet port on the reference carrier board. Table 2-1. GBE1 Signal Definitions...
  • Page 36 NI sbRIO-9651 System on Module Carrier Board Design Guide Table 2-1. GBE1 Signal Definitions (Continued) DIO Signal on Reference † Signal Name Pin # Carrier Board Direction Description GBE1_GMII_RX_D0 DIO_45_N Receive data GBE1_GMII_RX_D1 DIO_45 bus. GBE1_GMII_RX_D2 DIO_44 GBE1_GMII_RX_D3 DIO_44_N GBE1_GMII_RX_D4...

  • Page 37: Gbe1 Reference Schematic

    If you do not enable secondary Ethernet, you can use these pins for other FPGA DIO. † I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator.
  • Page 38 Figure 2-1. GBE1 Reference Schematic +1.8V 0.5% MDIA_P MDIA_N~ MDIB_P MDIB_N~ MDIC_P MDIC_N~ MDID_P +1.8 V +3.3 V MDID_N~ SHIELD1 MCTA +1.8V +1.8V +1.8V SHIELD2 DVDDH[0] AVDDH[0] +1.2 V MCTB DVDDH[1] AVDDH[1] MCTC GBE1_GMII_GTX_CLK DVDDH[2] R136 R137 +1.2 V MCTD AVDDL[0] 4.7 K 4.7 K...
  • Page 39 R202 49.9 0.5% DIO_50_N DIO_62_N GBE1_GMII_GTX_CLK 1/16 W 49.9 0.5% DIO_51 DIO_63_SRCC R209 1/16W DIO_51_N DIO_63_N GBE1_GMII_TX_D[1] 49.9 0.5% 1/16 W SBRIO-9651 Mating Connector Bank 2 - 4 of 6 Symbols R210 GBE1_GMII_TX_D[0] 49.9 0.5% 1/16 W 2-6 | ni.com...
  • Page 40 Signals, for information about the Gigabit Ethernet connector parts used in the sbRIO-9651 SOM development kit. • To meet GMII timing to the sbRIO-9651 SOM, the DIO bank for the PHY (DVDDH) and VIO_BANK2 on the sbRIO-9651 SOM must be powered at 1.8 V.

  • Page 41: Gbe1 Routing Considerations

    Chapter 1, requirements. Refer to the Ethernet Speed LED Behavior section of the Ethernet speed NI sbRIO-9651 System on Module OEM Device Specifications for LEDs information about Ethernet LED signal behavior and rated drive current. Ethernet link Figure 2-1 shows the logic required to create the same link activity activity LEDs LED behavior that the primary Ethernet signal uses.

  • Page 42: Additional Rs-232 (Serial2, Serial3, Serial4)

    CLIP Generator to configure these pins for any FPGA DIO. † I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator. © National Instruments | 2-9...

  • Page 43: Serial2 Reference Schematic

    Serial2 Reference Schematic Figure 2-3 shows a schematic design for the Serial2 implementation on the reference carrier board. Figure 2-3. Serial2 Reference Schematic C0603, SPARE C0603, SPARE C0603, SPARE +3.3V +3.3V C0603, SPARE 1800 PF 50 V R163 SERIAL2_SIGNAL_GND_232 C176 C171 C168 0.1 UF...

  • Page 44: Rs-485 (Serial5, Serial6)

    • FPGA DIO signals from DIO Bank 0 include series termination on the sbRIO-9651 SOM. Use series termination at the SEARAY connector on all signals outside of Bank 0 being driven from the sbRIO-9651 SOM to the serial transceiver. FPGA All serial port signals pass through the FPGA on the sbRIO-9651 SOM.

  • Page 45: Serial5 Definitions On The Reference Carrier Board

    CLIP Generator to configure these pins for any FPGA DIO. † I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator. 2-12 | ni.com...

  • Page 46: Serial5 Reference Schematic

    NI sbRIO-9651 System on Module Carrier Board Design Guide Serial5 Reference Schematic Figure 2-4 shows a schematic design for the Serial5 implementation on the reference carrier board. Figure 2-4. Serial5 Reference Schematic 0.1 uF and 0.01 uF 10 uF and 0.1 uF...

  • Page 47: Rs-485 Layout Considerations

    • FPGA DIO signals from DIO Bank 0 include series termination on the sbRIO-9651 SOM. Use series termination at the SEARAY connector on all signals outside of Bank 0 being driven from the sbRIO-9651 SOM to the serial transceiver. RS-485 Layout Considerations Pay close attention to how the ground planes are arranged under the isolated RS-485 transceiver.

  • Page 48: Can0 Signal Definitions On The Reference Carrier Board

    CLIP Generator to configure these pins for any FPGA DIO. † I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator. © National Instruments | 2-15...

  • Page 49: Can0 Reference Schematic

    Chapter 2 User-Defined FPGA Signals CAN0 Reference Schematic Figure 2-5 shows a schematic design for the CAN0 implementation on the reference carrier board. Figure 2-5. CAN0 Reference Schematic +3.3V C113 0.1 UF 0.1 UF 16 V 16 V CAN0_RX VCCB VCCA CAN0_RX_5V 49.9 0.5%...
  • Page 50 • U2, U4, and U6 provide level translation between the 3.3 V I/O on the CANx_RS sbRIO-9651 SOM and the 5 V I/O on the transceiver. Use caution when implementing this level translation. • The TXD and RS inputs of the CAN transceiver must remain high during power-down and power-up of the sbRIO-9651 SOM and carrier board.

  • Page 51: Termination Resistors For Can Cables

    Chapter 2 User-Defined FPGA Signals Termination Resistors for CAN Cables The termination resistors should match the nominal impedance of the CAN cable and therefore comply with the values in Table 2-9. Table 2-9. Termination Resistor Specification Characteristic Value Condition Termination resistor 100 Ω...

  • Page 52: Carrier Board Pcb Layout Guidelines

    Impedance-Controlled Signaling Use the following guidelines for implementing impedance for all I/O signals: • All signals connected to the sbRIO-9651 SOM must use impedance-controlled traces. Refer to the sections of this document listed in Table 3-1 for information about impedance requirements.

  • Page 53: Single-Ended Signal Best Practices

    FPGA DIO signals from DIO Bank 0 include series termination resistors near Note the Xilinx Zynq SoC on the sbRIO-9651 SOM. Refer to the FPGA DIO section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information.

  • Page 54: Ground And Power Plane Recommendations

    SOM must connect to the carrier board ground planes. • If possible, use planes to connect power to the sbRIO-9651 SOM. All power pins on the J1 connector of the sbRIO-9651 SOM must be connected and powered, even if a bank of DIO is unused.

  • Page 55: Mechanical Considerations

    SOM operating requirements. Mounting You can mount the sbRIO-9651 SOM and carrier board in a variety of ways in order to maximize system performance. Some mounting methods might require custom fasteners or unique assembly techniques to maintain required connector stack heights and enable improved thermal and structural design for rugged environments.

  • Page 56: Selecting Appropriate Standoffs

    NI requires that you use standoffs that are 0.15 mm (0.006 in.) taller than the combined height of the J1 connector on the sbRIO-9651 SOM and the mating SEARAY connector. Therefore, to determine the required standoff height, you must add the heights of the mated connectors plus an additional 0.15 mm (0.006 in.).
  • Page 57 NI sbRIO-9651 System on Module Carrier Board Design Guide Table 4-3 provides an example standoff height calculation using a Molex 45970-4130 mating connector. Table 4-3. Example Connector Configuration and Calculated Standoff Height Manufacturer, Component Part Number Height J1 connector on the sbRIO-9651 SOM Molex, 45971-4185 5.00 mm (0.197 in.)

  • Page 58: Mounting Direction Options

    Figures 4-1 through 4-3 show possible mounting configurations and associated fastener types. Mounting on a Panel or Plate (Recommended) If possible, NI recommends that you mount the sbRIO-9651 SOM on a panel or plate, as shown in Figure 4-1. Figure 4-1. Mounting on a Panel or Plate...
  • Page 59 This method accommodates a layer of thermal grease that is 0.08 mm (0.003 in.) thick between the aluminum heat spreader of the sbRIO-9651 SOM and the metal base panel. However, thicker thermal interface materials may require different lengths of standoffs or mounting bosses. The direction of fastening may also require custom lengths or types of fasteners and might impact ease of assembly.

  • Page 60: Managing Thermal Conditions

    Carrier board Managing Thermal Conditions Due to the compact size of the sbRIO-9651 SOM, it is very important to appropriately dissipate the heat generated during operation. You must plan for the thermal conditions of your application throughout development and validation. This section provides design recommendations and validation tools and methods for maximizing the thermal performance of the system.

  • Page 61: Understanding Thermal Specifications

    However, the 85 °C local ambient operating temperature rating of the sbRIO-9651 SOM does not mean that the external temperature of the natural convection environment such as a room or larger enclosure can be 85 °C.

  • Page 62: Validating The System

    • NI sbRIO device. This is measured on all sides of a device that has exposed circuitry. Because the sbRIO-9651 SOM has an integrated heat spreader on the primary side, only the secondary side needs to be measured. Because the system integrator may use any number of enclosure sizes, materials, thermal solutions, and room conditions when designing an enclosure for a specific application, NI sbRIO devices are specified in a manner that removes most of these external variables.
  • Page 63 This value is a conservative approximation of the local ambient temperature on that side of the circuit card assembly. To meet the thermal specifications described in the NI sbRIO-9651 System on Module OEM Device Specifications, you must record the following measurements: •...

  • Page 64: Managing Power And Feature Utilization

    Mechanical Considerations temperature. This alternative method provides a completely digital validation scheme that does not require using a thermocouple and allows you to validate the sbRIO-9651 SOM as part of every deployment. In addition to being useful for system validation, digitally reported temperatures also provide feedback about system health and can be used as triggers or set points.

  • Page 65: Mounting Recommendations For Maximizing Thermal Performance

    Mounting Recommendations for Maximizing Thermal Performance The sbRIO-9651 SOM includes an integrated heat spreader that uses a thermal gap filler material to effectively conduct into the spreader the heat that the circuit card assembly components generate. NI recommends the following mounting procedures for maximizing the thermal performance of your application: •...

  • Page 66: Additional Resources For Managing Thermal Conditions

    If this method is not feasible for your design, minimize the amount of extra mass that only the sbRIO-9651 SOM supports, such as a heat sink or other thermal solution, that is fastened to the four standoffs. If you require substantial thermal solutions, provide additional structural support.

  • Page 67: Reference Carrier Board Specifications And User Guide

    9651 and PCB gerber files. Parts Locator Diagram and Block Diagram Refer to the NI sbRIO-9651 System on Module Development Kit Quick Start Guide for the reference carrier board parts locator diagram and hardware block diagram. Specifications The following specifications are typical and not guaranteed.

  • Page 68: Ethernet

    Reference Carrier Board Specifications and User Guide Ethernet The reference carrier board includes the following tri-mode Ethernet ports: Ethernet0—Utilizes the primary Ethernet (GBE0) fixed behavior interface from the • sbRIO-9651 SOM. Ethernet1—Implemented from the secondary Ethernet user-defined FPGA interface. • Serial Number of ports...
  • Page 69 3.3 V Current 100 mA Pmod Signal Definitions on the Reference Carrier Board Table A-1 describes the pins and signals on the sbRIO-9651 SOM connector used to implement four Pmod 12-pin connectors. Pmod 12-Pin Connector Pinout Refer to the section of this chapter for more...

  • Page 70: Rtc Battery

    Appendix A Reference Carrier Board Specifications and User Guide Table A-2 describes the specific pins and signals on the sbRIO-9651 SOM connector used to implement a Pmod I C connector. Pmod I C Connector Pinout Refer to the section of this chapter for more...
  • Page 71 NI sbRIO-9651 System on Module Carrier Board Design Guide Table A-3. RS-232, RS-485, and CAN Port Pins and Signals TX/RX-only Full-modem RS-232 RS-232 RS-485 Signal Signal Signal Signal CANL SHIELD CANH Pmod 12-Pin Connector Pinout The Pmod 12-pin connectors on the reference carrier board use the port shown in Figure A-2.

  • Page 72: Pmod I 2 C Connector Pinout

    At the end of the product life cycle, all products must be sent to EU Customers a WEEE recycling center. For more information about WEEE recycling centers, National Instruments WEEE initiatives, and compliance with WEEE Directive 2002/96/EC on Waste and Electronic Equipment, visit ni.com/environment/...
  • Page 73 NI sbRIO-9651 System on Module Carrier Board Design Guide National Instruments (RoHS) National Instruments RoHS ni.com/ (For information about China RoHS compliance, environment/rohs_china go to ni.com/environment/rohs_china © National Instruments | A-7...

  • Page 74: Revision History

    Chapter 1, Behavior Signals. • Added more information about ordering the recommended mating connector Ordering (Molex, 45970-4130) from TTI, Inc. to the the Recommended Mating Connector section of Mechanical Considerations. Chapter 4, December 2014 — © National Instruments | B-1...
  • Page 75 NI Services National Instruments provides global services and support as part of our commitment to your success. Take advantage of product services in addition to training and certification programs that meet your needs during each phase of the application life cycle; from planning and development through deployment and ongoing maintenance.
  • Page 76 Appendix C NI Services Training and Certification—The NI training and certification program is the most • effective way to increase application development proficiency and productivity. Visit for more information. ni.com/training – The Skills Guide assists you in identifying the proficiency requirements of your current application and gives you options for obtaining those skills consistent with your time and budget constraints and personal learning preferences.

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