LG 60PC1D Training Presentation page 66

Input Voltages from the Y SUS Board
VS VS is supplied to IC7 and the SUS_IPM through coil FL5 and to the primary winding of
transformer T3 to the Z Bias Circuit. Input voltage measurement is made from connector
P12 pins 11 and 12, to chassis ground.
VA VA is supplied to the ER_HIGH IPM through resistor R10 and diode D18. VA voltage is also
routed to connectors P1 pin 5 and P9 pin 5 for the right top and bottom X driver boards.
5v 5v is used to Bias the circuits on the Z_ SUS Board. 5v also feeds connectors P1 pin 3 and P9
pin 3 for the right top and bottom X boards.
Voltages Developed on the Z SUS Board
Z Bias 165v is used to Bias the output circuits driving the Sustain and Erase Pulses, removing previous images
from the PDP. Z-bias is measured from the Vzb TP on the Z SUS Board and adjusted by VR3
IPM 18v IPM 18V needed to generate the Sustain and Erase pulses in the IPMs. Measured at positive side of Capacitor
C18 ( Located between the IPMs IC7 and IC3 ).
Plasma Display Panel Troubleshooting - 2007
60PC1D Z SUS Board
66
Troubleshooting