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2.2
Soldering Guidelines
Any solder re-work to modify the EVM for the purpose of repair or other application reasons must be
performed using a hot-air system to avoid damaging the integrated circuit (IC).
2.3
Equipment Interconnect
•
Set the input and bias power supply to 6.5 V(max). Turn the power supply off. Connect the positive
voltage lead from input power supply to VIN, at the J1 connector of the EVM. Connect the ground lead
from the input power supply to GND at the J2 connector of the EVM.
•
Connect a 0- to 2-A load between OUT and GND. The connector used depends on the desired output
current.
•
Disable the output by floating JP1.
3
Operation
•
Turn on the power supplies.
•
Enable the output by jumping JP1, the EN pin, to VIN or VBIAS.
•
Vary the respective load and input voltage as necessary for test purposes.
4
Thermal Guidelines and Layout Recommendations
Thermal management is a key component of design of any power converter and is especially important
when the power dissipation in the LDO is high. Use the following formulas to approximate the maximum
power dissipation for the particular ambient temperature:
x θ
T
= T
+ P
J
A
D
P
= (V
- V
D
IN
OUT1
Where T
is the junction temperature, T
J
device (Watts), and θ
Celsius. The maximum operating junction temperature, T
layout design must be copper trace and plane areas smartly, as thermal sinks, in order not to allow T
exceed the absolute maximum rating under all temperature conditions and voltage conditions across the
part.
Table 1
repeats information from the Dissipation Ratings Table of the TLV7163318 series data sheet for
comparison with the thermal resistance, θ
voltage can be calculated for full loads at different ambient temperatures. The input voltage must be less
than these values in order to maintain a safe junction temperature.
Table 1. Thermal Resistance, θ
IC
TPS7A8300
SLVU919 – June 2013
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JA
) × I
+ (V
- V
) × I
OUT1
IN
OUT2
OUT2
is the ambient temperature, P
A
is the thermal resistance from junction to ambient. All temperatures are in degrees
JA
, for High-K JEDEC standard boards. The maximum input
JA
Board
Package
High-K
RGW
Copyright © 2013, Texas Instruments Incorporated
is the power dissipation in the
D
must not be allowed to exceed 125°C. The
J,
, and Maximum Power Dissipation
JA
θ
Max Dissipation (T
JA
25°C)
35.7°C/W
2.80 W
TPS7A8300EVM-209 Evaluation Module
Operation
(1)
(2)
to
J
=
Max Dissipation @2A
A
(T
= 70°C)
A
1.54 W
3
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