Linear Technology DC1974 Series Demo Manual

DESCRIPTION
Demonstration circuit 1974 supports the LTC
dual ADC family with JESD204B compliant CML outputs.
It was specially designed for applications that require
single-ended AC coupled inputs. The DC1974 supports
the LTC2124, LTC2123 and
from 310Msps to 170Msps.
The specific ADC characteristics are listed in the DC1974
Variants section. The circuitry on the analog inputs is opti-
mized for analog input frequencies from 5MHz to 400MHz.
DC1974 VARIANTS
DC1974 VARIANTS
1974A-A
1974A-B
1974A-C
PERFORMANCE SUMMARY
PARAMETER
ADC Supply Voltage
Analog Input Range
Sampling Frequency (Device Clock Frequency)
Device Clock Level (Single-Ended at J3)
Device Clock Level (Differential Signal Across J3 and J4)
Digital Inputs (ADC_SYS_REF_N, ADC_SYS_REF_P,
SYNC_N, SYNC_P)
14-Bit, 310Msps to 170Msps Dual
2124 14-bit
®
LTC2122 with sample rates
ADC PART NUMBER
LTC2124
LTC2123
LTC2122
Specifications are at T
CONDITION
This Supply Must Provide Up to 700mA
Depending on ADC (1X CLK Mode)
Minimum Logic Levels (DEV
Maximum Logic Levels (DEV
Minimum Logic Levels (DEV
1.2V Common Mode)
Differential Input Voltage
Common Mode Input Range
DEMO MANUAL DC1974
LTC2124, LTC2123, LTC2122
ADCs with JESD204B Outputs
Refer to the data sheet for proper input networks for dif-
ferent input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1974
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
RESOLUTION MAXIMUM SAMPLE RATE
(Bit)
14
14
14
= 25°C
A
+ Tied to GND)
CLK
+ Tied to GND)
CLK
+ Not Tied to GND,
CLK
INPUT FREQUENCY
(Msps) (MHz)
310 5 to 400
250 5 to 400
170 5 to 400
MIN TYP MAX
4
1.35
10
0
0.2
0.2
1.1 1.2
UNIT
6 V
1.5 V
PP
310 MHz
V
3.6 V
V
1.8 V
1.5 V
dc1974f
1