Pcb Layout Guide; Stack-Up Options; Pcb Layout; Rf Trace - Sunsea AIoT SIMCom SIM5800 Hardware Design

5. PCB Layout Guide

Usually, most electronic products with good performance are based on good PCB layout. A bad PCB layout will
lead to lots of issues, like TDD noise, SIM card can not be detected, etc. The final solution for these problems is to
redo PCB layout. Making good PCB layout at beginning will save development schedule and cost as well.
This section as below will give some guidelines on PCB layout.
5.1

Stack-up Options

At least, 4-layer through-hole PCB should be chosen for good impedance control and signal shielding.
5.2

PCB Layout

Key points to note in the PCB layout phase:
5.2.1

RF Trace

 RF connector should be placed close to the module's antenna pin.

Antenna matching circuit should be placed close to the antenna.
 Keep the RF traces at 50Ω.

Maintain a complete and continuous reference ground plane from antenna pin to the RF connector.

The RF traces should be far away from any other noisy traces.

Keep the RF traces as short as possible.

If using a coaxial RF cable to connect the antenna, please avoid spanning on UIM cards, power circuits and
high-speed digital circuits to minimize the impact of each other.
5.2.2

POWER/GND


Both VBAT and return path should be as short and wide as possible .

The VBAT current should go through Zener diode, capacitors, then VBAT pins

Must have a solid ground plane throughout the board as the primary reference plane for most signals
5.2.3

USIM


Ensure UIM card holder is far way from antenna or RF signal

ESD component and bypass caps should be placed closed to UIM Card

UIM card signals should be far away from other high-speed signal
5.2.4

MIPI


Protect MIPI_DSI/CSI signals from noisy signals (clocks, SMPS, etc.)
 Differential pairs, 100 Ω nominal, ±10%

Total routing length < 305 mm

Intra-pair length matching < 5 ps (0.67 mm)

Inter-pair length matching < 10 ps (1.3 mm)

Lane-to-lane trace spacing = 3x line width

Spacing to all other signals = 4x line width

Maintain a solid ground reference for clocks to provide a low-impedance path for return currents

Each trace needs to be next to a ground plane

Minimize the number of via on the trace
About the length, please refer to the inner length of module in the following table to achieve the above
requirements:
Table 21: Line length of MIPI inside the module
SIM5800_Hardware Design_V1.01
Smart Machine Smart Decision
45 2018-10-08