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THEORY OF OPERA TlON
The fifth motor in the mechanism is a brush-type mode motor. This motor controls (selects) the mechanism
mode. Because the mode motor is not frequently used, the brush type motor is best suited to this application.
The mode motor performs the mode changes as directed; for example, this motor conditions the mechanism
to eject the cassette. The motor is controlled by a driver that receives instructions from mode motor
controller.
Servo Main Microprocessor and Servo Sub Microprocessor LSls
Two custom LSIs (84-pin, QFPs )--the Servo Main Microprocessor and Servo Sub Microprocessor---provide
the processing power for the various motion control circuits within the Python drives. The Drive Control Bus
connects these two LSIs with the SCSI controller circuits. These two microprocessor LSIs control all the
drive motors.
Read and Write LSls
Two single-chip signal processor and audio DAT-formatter LSIs provide the read and write signals for the
drive. Each LSI is supported by a 32-KB X 8 static RAM. These chips are controlled by the controller
microprocessor.
ATF Circuitry
The ATF circuitry of the Python drive is designed to provide high precision tracking and head positioning in
compliance with the ANSI DDS standard. The main component for ATF is a custom ATF LSI, which, in
conjunction with the four-head read-after-write (RAW) design, allows seamless appends, also in compliance
with the ANSI DDS standard.
A seamless append is the continuation of writing frames on the end-of-media (BOM) side of existing frames
(after a STOP) such that the tracks are placed as if they were in a continuous sequence. That is, the servo
system must be able to read the appended tracks without encountering discontinuity or gaps between tracks.
Performing a seamless append requires the highest precision and almost absolute accuracy in repositioning
the head assembly. In the Python products, this level of precision is attained through the combined accuracy
of the mechanical design and the ATF signal information as implemented through custom circuits.
SCSI Controller
The embedded SCSI controller circuitry in the Python drive is made up of several components. In the 3.5-
inch based 4322, 4542, and 4352 models, a single chip DDS formatter LSI communicates with the Servo
Main Microprocessor, Servo Sub Microprocessor, and Read and Write LSIs. The C3 ECC coprocessing
capability and the Memory Control function are also included in this single chip. Other components vital to
this circuitry are the high-performance SCSI LSI (NCR-53C96), the microprocessor (NEC V50), and the
EPROM (Intel 27C210). The standard dynamic RAM (DRAM) buffer is 512 KB; a 1-MB buffer is optional
on most models. Buffer parity checking is standard.
The AHA3101 data compression chip, which is a IOO-pin PQFP, is linked to the SCSI LSI (NCR-53C96) by
the Port A DMA interface of the AHA3101 chip. The SRAM (compression memory) external to the
AHA3101 chip is part of the SCSI controller circuitry. Refer to Section 7.3 for a more detailed discussion of
the AHA3101 data compression chip.
8-9
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