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hilscher NXHX 52-JTAG Device Description

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Device Description
NXHX 52-JTAG
Development Board
Hilscher Gesellschaft für Systemautomation mbH
www.hilscher.com
DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public

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Summary of Contents for hilscher NXHX 52-JTAG

  • Page 1 Device Description NXHX 52-JTAG Development Board Hilscher Gesellschaft für Systemautomation mbH www.hilscher.com DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public...

  • Page 2: Table Of Contents

    List of Revisions ....................4 1.1.2 Conventions in this Manual ..................5 1.1.3 Reference to Hardware ..................5 Other Relevant Documentation ..................6 DESCRIPTIONS AND DRAWINGS ................7 Description of the NXHX 52-JTAG ................7 Drawings........................8 2.2.1 Block Diagram ......................8 2.2.2 Printed Circuit Board ....................9 Operating Elements ....................11 2.3.1...
  • Page 3 TECHNICAL DATA ....................55 NXHX 52-JTAG ......................55 APPENDIX ........................56 Matrix Label ......................56 List of Figures ......................57 List of Tables ......................58 Contacts........................59 NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 4: Introduction

    Introduction 4/59 1 Introduction About This Manual This manual describes the NXHX 52-JTAG development board. 1.1.1 List of Revisions Index Date Chapter Revision 2013-02-20 Created 2013-03-21 2.3.2.1 Description of Host Interface Mode revised 2013-07-08 4.1.7 Section Accessory Cables and Connectors for Host Interface added.

  • Page 5: Conventions In This Manual

    1.1.3 Reference to Hardware Hardware Revision Part Number NXHX 52-JTAG 7773.300 Table 2: Reference to Hardware NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 6: Other Relevant Documentation

    Introduction 6/59 Other Relevant Documentation Besides this device description, the following documents are also relevant for the user of the NXHX 52-JTAG development board: Manual Contents Document Name NXHX 52-JTAG Describes typical use cases of the NXHX 52-JTAG Getting Started GS XX EN.pdf Getting Started Guide NXHX 52-JTAG Development Board.

  • Page 7: Descriptions And Drawings

    7/59 2 Descriptions and Drawings Description of the NXHX 52-JTAG The NXHX 52-JTAG is a development board for netX 52 and has the following functions:  Host interface, usable in different interface modes: 8/16/32 bit parallel dual-port memory, 16 bit TI multiplexed parallel dual-port memory, serial dual-port memory (SPI Slave), MII and PIO.

  • Page 8: Drawings

    Descriptions and Drawings 8/59 Drawings 2.2.1 Block Diagram Figure 1: NXHX 52-JTAG Block Diagram NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 9: Printed Circuit Board

    Descriptions and Drawings 9/59 2.2.2 Printed Circuit Board Figure 2: NXHX 52-JTAG Printed Circuit Board No. in Name Description For details see section Page figure Host interface Host Interface (X1) RJ45 Connector Ethernet interface CH1 2*RJ45 Ethernet Interface (X30) Matrix-Label...
  • Page 10 Configuration Host Mode - Switch Host Interface Mode / Boot Mode (S2) Table 4: List of Positions on Printed Circuit Board NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 11: Operating Elements

    Reset (T1) Function When button is pushed, system initiates power-on reset. Table 5: Push Button T1 Position in Figure 2: NXHX 52-JTAG Printed Circuit Board on page 9. 2.3.1.2 GPIO Input (T2) Function General purpose input with push button. Parallel to SD card detect switch. Switches high signal to MMIO09.

  • Page 12: Switches

    DPM_DIRQ# Table 7: Configuration - Switch S1, Boot Strap Options Position in Figure 2: NXHX 52-JTAG Printed Circuit Board on page 9. The boot mode and the host interface mode are evaluated by the ROM loader during boot. Boot Mode If S1.6 is ON and S1.1 and S1.2 are both set to OFF, the boot mode is read...
  • Page 13 Note: If you use boot mode 1, 2 or 4, set host interface mode to “Ignore host interface during boot” (see subsequent table). NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public...
  • Page 14 Reserved Do not use this setting! Table 9: Host Interface Mode at X1 (Settings) NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 15 SW 6 to OFF. Table 10: Configuration - Switch S2, Host Mode Position in Figure 2: NXHX 52-JTAG Printed Circuit Board on page 9. 2.3.2.3 Configuration RS Mode - Switch (S3) RS Mode, at connector X7 Signal...
  • Page 16 Figure 3: Block Diagram of the Driver and Receivers of X7 For more details, see data sheet of LTC 2870 at www.linear.com/product/LTC2870. NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 17: Interfaces

    Descriptions and Drawings 17/59 Interfaces 2.4.1 Host Interface (X1) Position in Figure 2: NXHX 52-JTAG Printed Circuit Board on page 9. 2.4.1.1 DPM and SDRAM Modes Signal Host Interface Modes SDRAM 32 Bit 32 Bit 8/16 Bit 16 Bit TI Multiplex...
  • Page 18 DPM_AD0 +3V3 PIO58 SDRAM_D20 DPM_D20 Table 14: Pin Assignment X1 Host Interface DPM and SDRAM Modes (Part 2) NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 19 EXT_D21 EXT_A17 EXT_A15 EXT_A14 EXT_A13 EXT_A12 Table 15: Pin Assignment X1 Host Interface Extension Bus Modes (Part 1) NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 20 EXT_D2 EXT_D1 EXT_D0 +3V3 EXT_D20 EXT_A16 Table 16: Pin Assignment X1 Host Interface Extension Bus Modes (Part 2) NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 21 RSTOUTn DPM_RESn MMIO03 MII_RXCLK MII_RXER MII_TXDCLK MII_TXDEN Table 17: Pin Assignment X1 Host Interface MII Mode (Part 1) NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 22 SPM or SPM_MISO MMIO40 MMIO +3V3 Table 18: Pin Assignment X1 Host Interface MII Mode (Part 2) NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 23: Mini-B Usb Connector (X3, 5 Pin)

    Power supply USB Bus (+5 V, from externally) Data - Data + Ground Table 19: Pin Assignment Mini-B USB Connector (5 pin) Position in Figure 2: NXHX 52-JTAG Printed Circuit Board on page 9. 2.4.3 D-Sub Connector 9 pin (X7) D-Sub- Signal Description RS232...

  • Page 24: Micro Sd Card Connector (X5)

    File names: 8.3 file format convention Table 21: Pin Assignment X5 micro SD Card Connector Position in Figure 2: NXHX 52-JTAG Printed Circuit Board on page 9. 2.4.5 Fieldbus Connector (X6 – 18 pin) Plug connector for additional fieldbus interface adapter, see also section Devices for Host Interface on page 29.

  • Page 25: Jtag Connector (X4)

    JT_TDO Table 23: Pin Assignment X4 JTAG Connector Position in Figure 2: NXHX 52-JTAG Printed Circuit Board on page 9. NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 26: Rj45 Ethernet Interface (X30)

    9. 2.4.8 Power Supply +24 V (X100) The NXHX 52-JTAG development board has to be supplied by DC. VIN is from 18 V to 30 V. The typical supply voltage is 24 V. Power consumption is approx. 2.6 W.

  • Page 27: Leds

    (off) Table 27: System Status LED Position in Figure 2: NXHX 52-JTAG Printed Circuit Board on page 9. NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 28: Using The Debugger

    28/59 3 Using the Debugger The NXHX 52-JTAG has a standard 20 pin JTAG connector, which can be used with any JTAG debug unit, like e. g. Tantino with HiTOP from hitex. The debug unit can be connected to the NXHX 52-JTAG connector X4 as...

  • Page 29: Accessories

    NXPCA-PCI NXHX 6-RE Figure 5: NXHX 52-JTAG with Possible Devices for the Host Interface and Fieldbus Modules If the NXHX 52-JTAG works as communication interface in DPM mode and a host is connected to X1, then S2.5 and S2.6 are closed and S1.7 and S1.8 are OFF.

  • Page 30: I/O Device At Host Interface (Nxhx-Io)

    LED 3 (PIO67) LED 14 (PIO78) +3.3 V The NXHX-IO must be operated in PIO mode! For this, the following settings of the switches on the NXHX 52-JTAG are necessary: S1.7 = OFF S2.1 = OFF S2.5 = ON NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public ©...

  • Page 31: Sdram Device At Host Interface (Nxhx-Sdr)

    SD_D21 SD_D0 +3.3 V SD_BA1 For operating the NXHX-SDR at the host interface, the following settings of the switches on the NXHX 52-JTAG are necessary: S1.7 = OFF S2.2 = OFF S2.3 = ON S2.4 = OFF S2.6 = ON...

  • Page 32: Phy And Serial Dual-Port Memory Device At Host Interface (Nxhx-Phy)

    Name Description 1 x RJ45 Connector Matrix label Host interface, soldered side AOI manufacturing label SPM Host interface NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 33 8 bit DPM mode Note that a switch for configuring the host mode is also implemented on the NXHX 52-JTAG development board, i. e. the S2 switch, which is described in the Configuration Host Mode - Switch (S2) section on page 15. The...

  • Page 34: Phy And Sdr Memory Device At Host Interface (Nxhx-Physdr)

    AOI manufacturing label. For operating the NXHX-PHYSDR at the host interface, the following settings of the switches on the NXHX 52-JTAG are necessary: S1.7 = OFF, S1.8 = OFF, S2.2 = OFF, S2.3 = ON, S2.4 = OFF, S2.6 = ON.

  • Page 35: Parallel Dual-Port Memory At Host Interface (Nxpca-Pci)

    35/59 4.1.5 Parallel Dual-Port Memory at Host Interface (NXPCA-PCI) The NXHX 52-JTAG can be accessed from the PC via the NXPCA-PCI Card, using the host interface as parallel dual-port memory. Figure 10: NXHX 52-JTAG connected to NXPCA-PCI Board Order Number of the NXPCA-PCI: 7902.100 See document: User Manual NXPCA-PCI_Rev_2_EN.pdf...

  • Page 36: Accessory Cables And Connectors For Host Interface

    The CAB-NXPCA-PCI cable can be used to connect the X3 host interface of the NXHX 51-ETM (see Host Interface (X1) section on page 17) with the Hilscher NXPCA-PCI Card (see Parallel Dual-Port Memory section on page 35) or other host devices.

  • Page 37: Fieldbus And Serial Adapters/Interfaces

    Receive- / Transmit data negative. 1, 2, 4, n.c. 6, 7, 9 9 pin, D-Sub, female Table 34: PROFIBUS RS-485 Pin Assignment NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 38: Nxhx-Co

    CAN H CAN High signal. DN V+ +24 V DeviceNet-power supply. COMBICON Socket, female Table 38: DeviceNet Pin Assignment NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 39: Nxhx-Rs

    Field ground, internally connected to SLD and COMBICON PE. Internally connected via 3,3 nF to DG. Socket, female Table 42: CC-Link Pin Assignment NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 40: Nxac-Power

    With barrel connector, sizes in mm Figure 12: Sizes of Barrel Connector NXAC-POWER Table 43: Technical Data Power Supply NXAC-POWER NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 41: Reference

    The following pages show the schematics for  NXHX 52-JTAG,  NXHX-IO,  NXHX-SDR,  NXHX-PHY and  NXHX-PHYSDR. NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 42 Reference 42/59 Figure 13: NXHX 52-JTAG Schematic – Host Interface NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 43 Reference 43/59 Figure 14: NXHX 52-JTAG Schematic – CPU Core NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 44 Reference 44/59 Figure 15: NXHX 52-JTAG Schematic – Ethernet Interface NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 45 Reference 45/59 Figure 16: NXHX 52-JTAG Schematic – Power Supply NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 46 Reference 46/59 Figure 17: NXHX-IO Schematic NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 47 Reference 47/59 Figure 18: NXHX-SDR Schematic NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 48 Reference 48/59 Figure 19: NXHX-PHY Schematic NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 49 Reference 49/59 Figure 20: NXHX-PHYSDR Schematic NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 50: Bill Of Materials

    DCDC-Converter SMD EN5312QIT Enpirion IC TXRX RS485/RS422 28-QFN LTC2870IUFD#PBF-ND LTC2870IUFD#PBF Linear Technologies CAN-Transceiver 3,3V SMD SN65HVD230DG4 Texas Instruments NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...
  • Page 51 USB MINI-B SMT MOLEX 675031020 Molex Western socket 8pol. 2 Ports angled TRJ26204BNL with magnetic module and LED green/yellow Trxcom Technology NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 52: Nxhx-Io

    GTFP08121HEU push/push with pull protection Amphenol strip 18pol. FJH Steckerverbindung GmbH D-Sub connector 9pol., SMD 7730P-09G2 SMD, SUYIN Suyin Table 44: Bill of Material NXHX 52-JTAG (7773.000 Revision 2) 5.2.2 NXHX-IO Schematics – Reference Description Quantity Manufacturer – Product Description Manufacturer...

  • Page 53: Nxhx-Phy

    203199 MJIM IM 1X1 S 88 GF5 Erni Strip 2*6 pin test XWLZ12SG Haxel Table 47: Bill of Material NXHX-PHY (7773.030 Revision 2) NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 54: Nxhx-Physdr

    LED Connector 68 pin 12C09-068SB SL-RM1,27-68 pin. (2x34) Haxel Table 48: Bill of Material NXHX-PHYSDR (7773.040 Revision 1) NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 55: Technical Data

    100 x 65 x 20 mm Operating Temperature 0 … 55 °C Table 49: Technical Data NXHX 52-JTAG NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 56: Appendix

    The figure shows part number 7773.000, hardware revision 2 and serial number 23457. Part number Hardware Revision Serial number Figure 21: Matrix Label NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

  • Page 57: List Of Figures

    Figure 3: Block Diagram of the Driver and Receivers of X7 Figure 4: Connecting the JTAG Debugger Figure 5: NXHX 52-JTAG with Possible Devices for the Host Interface and Fieldbus Modules Figure 6: NXHX-IO Printed Circuit Board Figure 7: NXHX-SDR Printed Circuit Board...

  • Page 58: List Of Tables

    Table 42: CC-Link Pin Assignment Table 43: Technical Data Power Supply NXAC-POWER Table 44: Bill of Material NXHX 52-JTAG (7773.000 Revision 2) Table 45: Bill of Material NXHX-IO (7703.010 Revision 2) Table 46: Bill of Material NXHX-SDR (7773.020 Revision 1) Table 47: Bill of Material NXHX-PHY (7773.030 Revision 2)

  • Page 59: Contacts

    Phone: +1 630-505-5301 E-Mail: info@hilscher.it E-Mail: info@hilscher.us Support Support Phone: +39 02 25007068 Phone: +1 630-505-5301 E-Mail: it.support@hilscher.com E-Mail: us.support@hilscher.com NXHX 52-JTAG | Development Board DOC120809HW06EN | Revision 6 | English | 2013-11 | Released | Public © Hilscher, 2012 - 2013...

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