Interrupt Assignment Of The Slot Connectors On The Bus Board - Siemens SIMATIC IPC847D Product Information

Interrupt assignment of the slot connectors on the bus board

Changes and supplements to section 8.5.2.3 of the operating instructions.
Note
All system resources (hardware addresses, memory allocation, interrupt assignment, DMA channels) are assigned
dynamically by the BIOS or the Windows operating system, depending on the hardware equipment, drivers, installed
expansion cards and connected external devices.
Assignment is automatic and depends on the demanded resources of the connected devices and the inserted modules. Due
to this configuration dependency, clear statements can only be made by determining them in relation to the system in the
final configuration. Resources may be viewed as follows under Windows:
1. Press the "Windows key" and "R" simultaneously.
The "Run" dialog box opens.
2. Enter "msinfo32" in the "Open" field.
3. Confirm your entry with "OK".
The following tables 1, 2 and 3 are examples of assignments if the system is operated in PIC mode (legacy mode).
The tables apply to the configuration with an expansion module which uses only one interrupt, e.g. PCI module which uses
the INTA# interrupt, connected to pin A6 of the PCI bus connector.
Bus board 7x PCI, 3x PCIe x4, 1x PCIe x16
Affected order numbers: 6AG4114-2xxx0-xxxx and 6AG4114-2xxx2-xxxx
Table 1
Slot 1 2
Type PCIe PCIe
4x 4x
PCH PCH
1 lane* 1 lane*
IRQ 0x05 0x0A
* Number of active PCIe lanes in the direct connector of the slot
Bus board 3x PCI, 3x PCIe x4, 5x PCIe x16
Affected order numbers: 6AG4114-2xxx1-xxxx and 6AG4114-2xxx3-xxxx
Table 2
Slot 1 2
Type PCIe PCIe
4x 4x
PCH PCH
4 lanes* 4 lanes*
switched switched
IRQ 0x0A 0x05
* Number of active PCIe lanes in the direct connector of the slot
** For details, see Table 3
SIMATIC IPC847D
A5E38018732-AD, 09/2017
3 4
PCIe
4x
PCH PCI PCI
1 lane*
0x0B 0x0B 0x0A
3 4
PCIe PCIe PCIe
4x x16 x16
PCH PCH PCH
4 lanes* 4 lanes* 4 lanes*
switched switched
switched
0x0B 0x0A 0x0A
5 6* 7**
PCIe
x16
PCI CPU
16
lanes*
0x05 0x05
5 6** 7**
PCIe PCIe
x16 x16
CPU CPU
4 lanes* 4 lanes*
See table 3
8** 9 10
PCI PCI PCI
behind behind behind
bridge bridge bridge
0x0A 0x0B 0x0A
8** 9 10
PCIe
x16
CPU PCI PCI
8 lanes*
0x0B 0x0B
11
PCI
behind
bridge
0x05
11
PCI
0x0B
23