Cypress enCoRe V LV CY7C60456 Manuals

Manuals and User Guides for Cypress enCoRe V LV CY7C60456. We have 1 Cypress enCoRe V LV CY7C60456 manual available for free PDF download: Technical Reference Manual

Cypress enCoRe V LV CY7C60456 Technical Reference Manual

Cypress enCoRe V LV CY7C60456 Technical Reference Manual (257 pages)

Brand: Cypress | Category: Single board computers | Size: 1 MB

Table of Contents

Table of Contents
3
Section A: Overview

9
- 1 Pin Information
  
  15
- Pinouts
  15
Section B: Encore V Core

23
- 2 CPU Core (M8C)
  
  26
  - Address Spaces
    26
  - Internal Registers
    26
  - Overview
    26
  - Instruction Set Summary
    27
  - Instruction Formats
    29
    
    One-Byte Instructions
    29
    
    Two-Byte Instructions
    29
    
    Three-Byte Instructions
    30
  - Register Definitions
    31
    
    CPU_F Register
    31
    
    Related Registers
    31
- 3 Supervisory ROM (SROM)
  
  32
  - Architectural Description
    32
    
    Additional SROM Feature
    33
    
    SROM Function Descriptions
    33
  - Register Definitions
    37
- 4 RAM Paging
  
  38
  - Architectural Description
    38
    
    Basic Paging
    38
    
    Stack Operations
    38
    
    Current
    39
    
    Interrupts
    39
    
    MVI Instructions
    39
    
    Index Memory
    40
  - Register Definitions
    41
    
    CUR_PP Register
    41
    
    Tmp_Drx Registers
    41
    
    IDX_PP Register
    42
    
    MVR_PP Register
    42
    
    STK_PP Register
    42
    
    MVW_PP Register
    43
    
    Related Registers
    43
- 5 Interrupt Controller
  
  44
  - Architectural Description
    44
    
    Posted Versus Pending Interrupts
    45
  - Application Overview
    45
  - Register Definitions
    46
    
    INT_CLR0 Register
    46
    
    INT_CLR1 Register
    47
    
    INT_CLR2 Register
    48
    
    INT_MSK0 Register
    49
    
    INT_MSK1 Register
    49
    
    INT_MSK2 Register
    50
    
    INT_SW_EN Register
    50
    
    INT_VC Register
    51
    
    Related Registers
    51
- 6 General-Purpose I/O (GPIO)
  
  52
  - Architectural Description
    52
    
    Analog and Digital Inputs
    53
    
    Digital I/O
    53
    
    General Description
    53
    
    Port 0 Distinctions
    53
    
    Port 1 Distinctions
    53
    
    GPIO Block Interrupts
    54
    
    Data Bypass
    55
  - Register Definitions
    56
    
    Prtxdr Registers
    56
    
    Prtxie Registers
    56
    
    Prtxdmx Registers
    57
    
    IO_CFG1 Register
    58
    
    IO_CFG2 Register
    58
- 7 Analog-To-Digital Converter (ADC)
  
  59
  - Architectural Description
    59
  - Brief Overview of ADC Components and Registers
    60
    
    Adc
    60
    
    Interface Command/Status Block
    60
  - ADC Register Definitions - Application Interface
    64
    
    ADC Data Register
    64
    
    ADC Status Register
    64
  - Application Overview
    65
    
    ADC Usage Guidelines
    65
    
    Status Codes
    65
    
    Use of Application Interface
    65
    
    Typical ADC Operation Procedure
    66
- 8 Internal Main Oscillator (IMO)
  
  67
  - Architectural Description
    67
  - Application Overview
    67
    
    Engaging Slow IMO
    67
    
    Trimming the IMO
    67
  - Register Definitions
    68
    
    IMO_TR Register
    68
    
    IMO_TR1 Register
    68
    
    CPU_SCR1 Register
    69
    
    OSC_CR2 Register
    69
    
    Related Registers
    69
  - Timing Diagrams
    69
  - Clocking Strategy
    70
  - Usage Guidelines
    70
    
    Power down Guidelines
    70
  - Block Size/Area
    70
  - Gate Count
    70
  - Block Pin List
    70
  - Block Level Interfaces
    70
  - Initialization
    70
  - Wounding
    70
  - On-Chip Debugger Modes
    70
  - Operating Condition Requirements
    71
  - DC Specifications
    71
  - AC Specifications
    71
- 9 Internal Low-Speed Oscillator (ILO)
  
  72
  - Architectural Description
    72
  - Register Definitions
    73
    
    ILO_TR Register
    73
- 10 External Crystal Oscillator (ECO)
  
  74
  - Architectural Description
    74
  - Application Overview
    75
  - Register Definitions
    76
    
    ECO_CFG Register
    76
    
    ECO_ENBUS Register
    76
    
    ECO_TRIM Register
    76
    
    Related Registers
    77
  - Usage Modes and Guidelines
    77
- 11 Sleep and Watchdog
  
  78
  - Architectural Description
    78
    
    Sleep Control Implementation Logic
    79
    
    Sleep Timer
    81
  - Application Overview
    81
  - Register Definitions
    82
    
    RES_WDT Register
    82
    
    SLP_CFG Register
    82
    
    Related Registers
    83
    
    SLP_CFG2 Register
    83
    
    SLP_CFG3 Register
    83
  - Timing Diagrams
    84
    
    Sleep Sequence
    84
    
    Bandgap Refresh
    85
    
    Wakeup Sequence
    85
    
    Watchdog Timer
    86
- 12 Regulated I/O
  
  87
  - Architectural Description
    87
    
    Bias Generator
    88
    
    Charge Pump
    88
    
    Comparator
    88
    
    Pass Transistors
    88
    
    Replica Structure
    88
  - Application Overview
    88
  - Register Definitions
    89
    
    IO_CFG1 Register
    89
    
    IO_CFG2 Register
    89
- 13 I/O Analog Multiplexer
  
  90
  - Architectural Description
    90
  - Register Definitions
    91
    
    Mux_Crx Registers
    91
Section C: System Resources

92
- 14 Digital Clocks
  
  96
  - Architectural Description
    96
    
    Internal Low-Speed Oscillator
    96
    
    Internal Main Oscillator
    96
    
    External Clock
    97
  - Register Definitions
    99
    
    OUT_P1 Register
    99
    
    USB_MISC_CR Register
    99
    
    OSC_CR0 Register
    101
    
    OSC_CR2 Register
    102
- 15 I C Slave
  
  103
  - I 2 C Slave
    103
    
    Architectural Description
    103
    
    Basic I 2 C Data Transfer
    104
    
    Application Overview
    105
    
    Slave Operation
    105
    
    I2C_ADDR Register
    106
    
    I2C_XCFG Register
    106
    
    Register Definitions
    106
    
    I2C_CFG Register
    107
    
    I2C_SCR Register
    109
    
    I2C_DR Register
    110
    
    Basic I/O Timing
    111
    
    Clock Generation
    111
    
    Timing Diagrams
    111
    
    Status Timing
    112
    
    Slave Stall Timing
    113
- 16 System Resets
  
  114
  - Architectural Description
    114
  - Pin Behavior During Reset
    114
    
    GPIO Behavior on Power up
    114
    
    GPIO Behavior on External Reset
    115
    
    Powerup External Reset Behavior
    115
  - Register Definitions
    116
    
    CPU_SCR1 Register
    116
    
    CPU_SCR0 Register
    117
  - Timing Diagrams
    118
    
    External Reset
    118
    
    Power-On-Reset
    118
    
    Watchdog Timer Reset
    118
    
    Reset Details
    120
  - Power Modes
    120
- 17 Por and LVD
  
  121
  - Architectural Description
    121
  - Register Definitions
    122
    
    VLT_CMP Register
    122
    
    VLT_CR Register
    122
- 18 Spi
  
  123
  - Architectural Description
    123
    
    SPI Protocol Function
    123
    
    SPI Master Function
    124
    
    SPI Slave Function
    124
    
    Input Synchronization
    125
  - Register Definitions
    125
    
    SPI_TXR Register
    125
    
    SPI_RXR Register
    126
    
    SPI_CR Register
    127
    
    Related Registers
    128
    
    SPI_CFG Register
    128
  - Timing Diagrams
    129
    
    SPI Mode Timing
    129
    
    SPIM Timing
    130
    
    SPIS Timing
    134
- 19 Programmable Timer
  
  137
  - Architectural Description
    137
    
    Operation
    137
  - Register Definitions
    139
    
    PT0_CFG Register
    139
    
    PT1_CFG Register
    139
    
    PT2_CFG Register
    140
    
    Ptx_Data0 Register
    140
    
    Ptx_Data1 Register
    140
- 20 Full-Speed USB
  
  141
  - Architectural Description
    141
  - Application Description
    141
    
    Usb Sie
    141
    
    Usb Sram
    142
    
    Oscillator Lock
    144
    
    Transceiver
    144
    
    Regulator
    145
    
    USB Suspend
    145
  - Register Definitions
    147
    
    USB_CR0 Register
    147
    
    USB_SOF0 Register
    147
    
    USBIO_CR0 Register
    148
    
    USBIO_CR1 Register
    148
    
    EP0_CR Register
    149
    
    EP0_CNT Register
    150
    
    Ep0_Drx Register
    150
    
    Epx_Cnt1 Register
    151
    
    Epx_Cnt0 Register
    152
    
    Epx_Cr0 Register
    153
    
    Pmax_Wa Register
    154
    
    Pmax_Dr Register
    155
    
    Pmax_Ra Register
    156
    
    USB_CR1 Register
    157
    
    USB_MISC_CR Register
    157
    
    IMO_TR1 Register
    158
Section D: Registers

159
- 21 Register Reference
  
  163
- Maneuvering Around the Registers
  163
- Register Conventions
  163
- Bank 0 Registers
  164
- Bank 1 Registers
  212
Section E: Glossary

239

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