User Manuals: Cypress PSoC CY8C23433 System-on-Chip

Manuals and User Guides for Cypress PSoC CY8C23433 System-on-Chip. We have 1 Cypress PSoC CY8C23433 System-on-Chip manual available for free PDF download: Technical Reference Manual

Cypress PSoC CY8C23433 Technical Reference Manual

Cypress PSoC CY8C23433 Technical Reference Manual (410 pages)

Brand: Cypress | Category: Single board computers | Size: 2 MB

Table of Contents

Table of Contents
3
Section A: Overview

17
- Document Organization
  17
- Top-Level Architecture
  18
- Psoc Core
  18
- Digital System
  18
- Analog System
  18
- System Resources
  18
- Psoc Device Characteristics
  20
- Psoc Device Distinctions
  20
- Getting Started
  21
- Support
  21
- Product Upgrades
  21
- Development Kits
  21
- Document History
  21
- Documentation Conventions
  22
- Register Conventions
  22
- Numeric Naming
  22
- Units of Measure
  22
- Acronyms
  23
- Pin Information
  25
- Pinouts
  25
- 28-Pin Part Pinout
  26
- 32-Pin Part Pinout
  28
- 56-Pin Part Pinout
  29
Section B: Psoc Core

31
- Top-Level Core Architecture
  31
- Interpreting Core Documentation
  31
- Core Register Summary
  32
- CPU Core (M8C)
  35
- Overview
  35
- Internal Registers
  35
- Address Spaces
  35
- Instruction Set Summary
  36
- Instruction Formats
  38
- One-Byte Instructions
  38
- Two-Byte Instructions
  38
- Three-Byte Instructions
  39
- Addressing Modes
  39
- Source Immediate
  39
- Source Direct
  40
- Source Indexed
  40
- Destination Direct
  41
- Destination Indexed
  41
- Destination Direct Source Immediate
  41
- Destination Indexed Source Immediate
  42
- Destination Direct Source Direct
  42
- Source Indirect Post Increment
  43
- Destination Indirect Post Increment
  43
- Register Definitions
  44
- CPU_F Register
  44
- Supervisory ROM (SROM)
  45
- Architectural Description
  45
- Additional SROM Feature
  46
- SROM Function Descriptions
  46
- Swbootreset Function
  46
- Readblock Function
  47
- Writeblock Function
  48
- Eraseblock Function
  48
- Protectblock Function
  49
- Tableread Function
  49
- Eraseall Function
  49
- Checksum Function
  50
- Calibrate0 Function
  50
- Calibrate1 Function
  50
- Register Definitions
  51
- CPU_SCR1 Register
  51
- FLS_PR1 Register
  52
- Clocking
  53
- DELAY Parameter
  53
- CLOCK Parameter
  53
- RAM Paging
  55
- Architectural Description
  55
- Basic Paging
  55
- Stack Operations
  56
- Interrupts
  56
- MVI Instructions
  56
- Current
  56
- Index Memory
  57
- Register Definitions
  58
- Tmp_Drx Registers
  58
- CPU_F Register
  59
- Interrupt Controller
  61
- Architectural Description
  61
- Posted Versus Pending Interrupts
  62
- Application Description
  63
- Register Definitions
  64
- Int_Clrx Registers
  64
- INT_CLR0 Register
  64
- INT_CLR1 Register
  65
- INT_CLR3 Register
  65
- Int_Mskx Registers
  65
- INT_MSK3 Register
  65
- INT_MSK0 Register
  66
- INT_MSK1 Register
  66
- INT_VC Register
  66
- CPU_F Register
  67
- General Purpose IO (GPIO)
  69
- Architectural Description
  69
- Digital IO
  69
- Global IO
  70
- Analog Input
  70
- GPIO Block Interrupts
  71
- Register Definitions
  72
- Prtxdr Registers
  72
- Prtxie Registers
  72
- Prtxgs Registers
  73
- Prtxdmx Registers
  74
- Prtxicx Registers
  75
- Analog Output Drivers
  77
- Architectural Description
  77
- Register Definitions
  78
- ABF_CR0 Register
  78
- Internal Main Oscillator (IMO)
  79
- Architectural Description
  79
- Application Description
  79
- Trimming the IMO
  79
- Register Definitions
  80
- CPU_SCR1 Register
  80
- OSC_CR2 Register
  81
- IMO_TR Register
  81
- Internal Low Speed Oscillator (ILO)
  83
- Architectural Description
  83
- Register Definitions
  83
- ILO_TR Register
  83
- External Crystal Oscillator (ECO)
  85
- Architectural Description
  85
- ECO External Components
  86
- Psoc Device Distinctions
  86
- Register Definitions
  87
- CPU_SCR1 Register
  87
- OSC_CR0 Register
  88
- ECO_TR Register
  89
- Phase-Locked Loop (PLL)
  91
- Architectural Description
  91
- Register Definitions
  91
- OSC_CR0 Register
  92
- OSC_CR2 Register
  93
- Sleep and Watchdog
  95
- Architectural Description
  95
- 32 Khz Clock Selection
  95
- Sleep Timer
  95
- Application Description
  96
- Register Definitions
  97
- INT_MSK0 Register
  97
- RES_WDT Register
  97
- CPU_SCR1 Register
  98
- CPU_SCR0 Register
  99
- OSC_CR0 Register
  100
- ILO_TR Register
  101
- ECO_TR Register
  101
- Timing Diagrams
  102
- Sleep Sequence
  102
- Wake up Sequence
  103
- Bandgap Refresh
  104
- Watchdog Timer
  104
- Power Consumption
  105
Section C: Register Reference

107
- Register General Conventions
  107
- Register Naming Conventions
  107
- Register Mapping Tables
  107
- Register Map Bank 0 Table: User Space
  108
- Register Map Bank 1 Table: Configuration Space
  109
- Register Details
  111
- Maneuvering Around the Registers
  111
- Register Conventions
  112
- Register Naming Conventions
  112
- Bank 0 Registers
  113
- Prtxdr
  113
- Prtxie
  114
- Prtxgs
  115
- Prtxdm2
  116
- Dxbxxdr0
  117
- Dxbxxdr1
  118
- Dxbxxdr2
  119
- Dxbxxcr0 (Timer Control)
  120
- Dxbxxcr0 (Counter Control)
  121
- Dxbxxcr0 (Dead Band Control)
  122
- Dxbxxcr0 (CRCPRS Control)
  123
- Dcbxxcr0 (SPIM Control)
  124
- Dcbxxcr0 (SPIS Control)
  125
- Dcbxxcr0 (UART Transmitter Control)
  126
- Dcbxxcr0 (UART Receiver Control)
  127
- Amx_In
  128
- Arf_Cr
  129
- Cmp_Cr0
  130
- Asy_Cr
  131
- Cmp_Cr1
  132
- Saradc_Dl
  133
- Saradc_Cr0
  134
- Saradc_Cr1
  135
- Tmp_Drx
  136
- Acbxxcr3
  137
- Acbxxcr0
  138
- Acbxxcr1
  140
- Acbxxcr2
  142
- Asdxxcr0
  143
- Asdxxcr1
  144
- Asdxxcr2
  145
- Asdxxcr3
  146
- Ascxxcr0
  147
- Ascxxcr1
  148
- Ascxxcr2
  149
- Ascxxcr3
  150
- Rdixri
  151
- Rdixsyn
  152
- Rdixis
  153
- Rdixlt0
  154
- Rdixlt1
  155
- Rdixro0
  156
- Rdixro1
  157
- I2C_Cfg
  158
- I2C_Scr
  159
- I2C_Dr
  161
- I2C_Mscr
  162
- Int_Clr0
  163
- Int_Clr1
  165
- Int_Clr3
  166
- Int_Msk3
  167
- Int_Msk0
  168
- Int_Msk1
  169
- Int_Vc
  170
- Res_Wdt
  171
- Dec_Dh
  172
- Dec_Dl
  173
- Dec_Cr0
  174
- Dec_Cr1
  175
- Mulx_X
  176
- Mulx_Y
  177
- Mulx_Dh
  178
- Mulx_Dl
  179
- Macx_X/Accx_Dr1
  180
- Macx_Y/Accx_Dr0
  181
- Macx_Cl0/Accx_Dr3
  182
- Macx_Cl1/Accx_Dr2
  183
- Cpu_F
  184
- Cpu_Scr1
  185
- Cpu_Scr0
  186
- Bank 1 Registers
  187
- Prtxdm0
  187
- Prtxdm1
  188
- Prtxic0
  189
- Prtxic1
  190
- Dxbxxfn
  191
- Dxbxxin
  193
- Dxbxxou
  195
- Clk_Cr0
  197
- Clk_Cr1
  198
- Abf_Cr0
  199
- Amd_Cr0
  200
- Amd_Cr1
  201
- Alt_Cr0
  202
- Saradc_Trs
  203
- Saradc_Trcl
  204
- Saradc_Trch
  205
- Saradc_Cr2
  206
- Saradc_Lcr
  207
- Gdi_O_In
  208
- Gdi_E_In
  209
- Gdi_O_Ou
  210
- Gdi_E_Ou
  211
- Osc_Go_En
  212
- Osc_Cr4
  213
- Osc_Cr3
  214
- Osc_Cr0
  215
- Osc_Cr1
  216
- Osc_Cr2
  217
- Vlt_Cr
  218
- Vlt_Cmp
  219
- Imo_Tr
  220
- Ilo_Tr
  221
- Bdg_Tr
  222
- Eco_Tr
  223
- Fls_Pr1
  224
Section D: Digital System

225
- Top-Level Digital Architecture
  225
- Interpreting the Digital Documentation
  225
- Digital Register Summary
  226
- Global Digital Interconnect (GDI)
  229
- Architectural Description
  229
- 28-Pin Global Interconnect
  230
- Register Definitions
  231
- Gdi_X_In Registers
  231
- Gdi_X_Ou Registers
  232
- Array Digital Interconnect (ADI)
  233
- Architectural Description
  233
- Row Digital Interconnect (RDI)
  235
- Architectural Description
  235
- Register Definitions
  237
- Rdixri Register
  237
- Rdixsyn Register
  237
- Rdixis Register
  238
- Rdixltx Registers
  239
- Rdixrox Registers
  240
- Rdixro0 Register
  240
- Rdixro1 Register
  240
- Timing Diagram
  240
- Digital Blocks
  241
- Architectural Description
  241
- Input Multiplexers
  242
- Input Clock Resynchronization
  242
- Clock Resynchronization Summary
  243
- Output De-Multiplexers
  243
- Block Chaining Signals
  243
- Input Data Synchronization
  243
- Timer Function
  243
- Usability Exceptions
  243
- Block Interrupt
  243
- Counter Function
  244
- Usability Exceptions
  244
- Block Interrupt
  244
- Dead Band Function
  244
- Usability Exceptions
  245
- Block Interrupt
  245
- CRCPRS Function
  245
- Usability Exceptions
  246
- Block Interrupt
  246
- SPI Protocol Function
  247
- SPI Protocol Signal Definitions
  247
- SPI Master Function
  247
- Usability Exceptions
  248
- Block Interrupt
  248
- SPI Slave Function
  248
- Asynchronous Transmitter and Receiver Functions
  249
- Asynchronous Transmitter Function
  249
- Usability Exceptions
  249
- Block Interrupt
  249
- Asynchronous Receiver Function
  249
- Usability Exceptions
  250
- Block Interrupt
  250
- Register Definitions
  251
- Dxbxxdrx Registers
  252
- Timer Register Definitions
  252
- Counter Register Definitions
  253
- Dead Band Register Definitions
  253
- CRCPRS Register Definitions
  254
- SPI Master Register Definitions
  254
- SPI Slave Register Definitions
  255
- Transmitter Register Definitions
  255
- Receiver Register Definitions
  255
- Dxbxxcr0 Register
  256
- INT_MSK1 Register
  257
- Dxbxxfn Registers
  257
- Dxbxxin Registers
  259
- Dxbxxou Registers
  260
- Timing Diagrams
  262
- Timer Timing
  262
- Counter Timing
  263
- Dead Band Timing
  264
- Changing the PWM Duty Cycle
  264
- Kill Operation
  265
- CRCPRS Timing
  266
- SPI Mode Timing
  266
- SPIM Timing
  267
- SPIS Timing
  270
- Transmitter Timing
  273
- Receiver Timing
  275
Section E: Analog System

279
- Top-Level Analog Architecture
  279
- Interpreting the Analog Documentation
  279
- Application Description
  280
- Defining the Analog Blocks
  280
- Analog Functionality
  280
- Analog Register Summary
  281
- Analog Interface
  283
- Architectural Description
  283
- Analog Data Bus Interface
  284
- Analog Comparator Bus Interface
  284
- Analog Column Clock Generation
  285
- Column Clock Synchronization
  285
- Decimator and Incremental ADC Interface
  285
- Decimator
  285
- Incremental ADC
  285
- Analog Modulator Interface (Mod Bits)
  286
- Analog Synchronization Interface (Stalling)
  286
- Psoc Device Distinctions
  286
- Application Description
  286
- SAR Hardware Acceleration
  286
- Architectural Description
  287
- Application Description
  287
- SAR Timing
  290
- Register Definitions
  291
- ASY_CR Register
  291
- CMP_CR1 Register
  292
- DEC_CR0 Register
  293
- DEC_CR1 Register
  293
- CLK_CR0 Register
  294
- CLK_CR1 Register
  294
- AMD_CR0 Register
  295
- AMD_CR1 Register
  295
- ALT_CR0 Register
  295
- Analog Array
  297
- Architectural Description
  297
- Nmux Connections General Overview
  298
- Pmux Connections General Overview
  299
- Rbotmux Connections General Overview
  300
- Amux Connections General Overview
  301
- Cmux Connections General Overview
  302
- Bmux SC/SD Connections General Overview
  303
- Analog Comparator Bus
  303
- Temperature Sensing Capability
  303
- Analog Input Configuration
  305
- Architectural Description
  305
- Two Column Analog Input Configuration
  306
- Register Definitions
  307
- AMX_IN Register
  307
- ABF_CR0 Register
  307
- Analog Reference
  309
- Architectural Description
  309
- Register Definitions
  310
- ARF_CR Register
  310
- Continuous Time Psoc Block
  313
- Architectural Description
  313
- Register Definitions
  315
- Acbxxcr3 Register
  315
- Acbxxcr0 Register
  317
- Acbxxcr1 Register
  317
- Acbxxcr2 Register
  318
- Switched Capacitor Psoc Block
  319
- Architectural Description
  319
- Application Description
  321
- Register Definitions
  322
- Ascxxcr0 Register
  323
- Ascxxcr1 Register
  324
- Ascxxcr2 Register
  324
- Ascxxcr3 Register
  325
- Asdxxcr0 Register
  326
- Asdxxcr1 Register
  327
- Asdxxcr2 Register
  327
- Asdxxcr3 Register
  328
- SAR8 ADC Psoc Block
  329
- Architectural Description
  329
- Features
  329
- Register Definitions
  330
- SARADC_DL Register
  330
- SARADC_CR0 Register
  330
- SARADC_CR1 Register
  331
- SARADC_TRS Register
  332
- SARADC_TRCL Register
  333
- SARADC_TRCH Register
  333
- SARADC_CR2 Register
  334
- SARADC_LCR Register
  334
Section F: System Resources

335
- Top-Level System Resources Architecture
  335
- Interpreting the System Resources Documentation
  335
- System Resources Register Summary
  336
- Digital Clocks
  339
- Architectural Description
  339
- Internal Main Oscillator
  339
- Internal Low Speed Oscillator
  339
- Khz Crystal Oscillator
  341
- External Clock
  341
- Clock Doubler
  341
- Switch Operation
  341
- Psoc Device Distinctions
  342
- Register Definitions
  343
- INT_CLR0 Register
  343
- INT_MSK0 Register
  343
- OSC_GO_EN Register
  344
- OSC_CR4 Register
  344
- OSC_CR3 Register
  345
- OSC_CR0 Register
  346
- OSC_CR1 Register
  347
- OSC_CR2 Register
  348
- Multiply Accumulate (MAC)
  349
- Architectural Description
  349
- Application Description
  350
- Multiplication with no Accumulation
  350
- Accumulation after Multiplication
  350
- Register Definitions
  351
- Mulx_X Register
  351
- Mulx_Y Register
  351
- Mulx_Dh Register
  352
- Mulx_Dl Register
  352
- Macx_X/Accx_Dr1 Register
  352
- Macx_Y/Accx_Dr0 Register
  353
- Macx_Cl0/Accx_Dr3 Register
  353
- Macx_Cl1/Accx_Dr2 Register
  353
- Decimator
  355
- Architectural Description
  355
- Decimator Block
  355
- Register Definitions
  357
- DEC_DH Register
  357
- DEC_DL Register
  357
- DEC_CR0 Register
  358
- DEC_CR1 Register
  358
- I2C
  359
- Architectural Description
  359
- Basic I2C Data Transfer
  359
- Application Description
  360
- Slave Operation
  360
- Master Operation
  361
- Register Definitions
  362
- I2C_CFG Register
  362
- I2C_SCR Register
  364
- I2C_DR Register
  366
- I2C_MSCR Register
  366
- Timing Diagrams
  368
- Clock Generation
  368
- Basic Input/Output Timing
  368
- Status Timing
  369
- Master Start Timing
  370
- Master Restart Timing
  371
- Master Stop Timing
  371
- Master/Slave Stall Timing
  372
- Master Lost Arbitration Timing
  372
- Master Clock Synchronization
  373
- Internal Voltage Reference
  375
- Architectural Description
  375
- Register Definitions
  376
- BDG_TR Register
  376
- System Resets
  377
- Architectural Description
  377
- Pin Behavior During Reset
  377
- GPIO Behavior on Power up
  377
- Register Definitions
  378
- CPU_SCR1 Register
  378
- CPU_SCR0 Register
  379
- Timing Diagrams
  380
- Power on Reset
  380
- Watchdog Timer Reset
  380
- Reset Details
  382
- Power Consumption
  382
- POR and LVD
  383
- Architectural Description
  383
- Register Definitions
  384
- VLT_CR Register
  384
- VLT_CMP Register
  384
- Section G: Glossary
  385
- Index
  401

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