HP 743 Series Technical Reference Manual For Oems page 33

General Information
Model 743 and Model 744 VME Board Computers
The VME controller ASIC supports the following additional features:
Table 1-21 summarizes VME performance. The values shown in this table reflect raw hard-
ware speed and do not include software overhead or system overhead.
Table 1-21 VME Performance in MB/sec
Master
Slave
Interval Timers
provide interrupts on terminal count and interrupt and restart on terminal count capability.
Table 1-22 summarizes the specifications for the interval timer.
Table 1-22 Interval Timer Specifications
Resolution
Timer 1 length
Timer 2 length
Timer 3 length
Watchdog Timer
HP-RT operating system.
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• 16 deep by 1 byte message FIFO with interrupt on not empty
256 µs arbitration timer
•
• Ability to generate interrupts on any one of IRQ1 to IRQ7; programmable IACK status/ID.
• Automatic slot 1 detect by way of sensing VME BGIN[3] at power up.
• DMA controller with programmable bus tenure
• Independent location monitor
• IRQ1 to IRQ7 interrupt handling individually programmable.
• Programmable BR0 to BR3 levels (processor and DMA programmed separately)
Programmable bus error timer from 10 µs to 1.28 ms
•
• Programmable request mode: ROR, RWD, RWD/Fair
• Reception of read-modify-write cycles (Software protocol must be enforced for processor
accesses to insure mutual exclusivity.)
• Selective generation of read-modify-write cycles
• Slot 1 arbiter programmable for RR or PRI bus arbitration
• VME64 "lock" address modifier cycles
D32 MBLT
Read Write Read
10 12 38
9 13 33
Three interval timers are part of the VME controller ASIC. These timers
Drift
32 bits, cascadeable into timer 2
16 bits, cascadeable into timer 3
16 bits
The VME controller ASIC also includes a watchdog timer used with the
Write
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