HP 743 Series Technical Reference Manual For Oems page 147

Product Design Considerations
Application Information
In a combined Models 742i and 747i and Models 743i and 748i backplane containing one or
more Models 742i and 747i VME ASICS, the address areas previously discussed must be
unpopulated to avoid conflicts prior to loading the operating system. The lowest 256 MB
region should be left unused for system use. For more information on combined systems,
refer to /etc/vme/example2.CFG and the HP-RT System Administrator Task Manual.
The VME ASIC in the Models 743i and 744 does not respond to VME cycles until it is
explicitly enabled by the HP-UX operating system.
VME ASIC VME Sysreset Behavior
When the VME ASIC is a slot 1 controller (always on the Model 747i and switch selectable
on the Model 742i/rt), it generates VME sysreset and VME sysfail at power on, but ignores
the state of these lines thereafter. If the VME ASIC is not a slot 1 controller, assertion of
VME sysreset by another VME card causes the Model 742i/rt to reboot.
The VME ASIC in the Models 743i and 744 behaves similarly but can be configured as to
whether or not a VME sysreset causes a non slot 1 controller to reboot.
Models 742i and 747i VME IACK Anomaly at Power On
Models 742i and 747i respond to the first interrupt cycle on any irq level after power-on with
an invalid status-id by the VME ASIC. This behavior occurs regardless of whether or not
Models 742i or 747i are enabled as an interrupt handler for the associated interrupt level. The
patched HP-UX Version 9.05 fixes this behavior; however, the behavior should not cause
problems because VME handles multiple interrupts on an irq level.
Models 743i and 744 do not exhibit this behavior.
VME System Configuration Information
The HP-UX vme_config program helps system integrators generate a conflict-free system
configuration. After running vme_config, which writes data into the EEPROM, the system
must be rebooted to use the new EEPROM information. For more information, refer to
"Required Entity Declarations for HP Processors" in /etc/vme/example(x).CFG and the HP-
UX 10.0 VME Device Drivers Manual.
Runtime VME ASIC Anomalies
The VME data lines need to remain stable during the entire write cycle from a non-743/744
VME bus master to the main memory of Models 743i or 744 serving as a VME slave. The
write cycle includes the time from the assertion of the data strobe by the master to the receipt
of DTACK from Model 743/744. All data lines need to remain stable in all transactions,
including higher order data lines unused in a D08 or D16 data transaction.
NOTE: If the VMEbus card bus master either drives the data lines to a known and stable state or allows
the data lines to float to VME's stable high termination, there will be no parity errors. However,
if the VMEbus card master drives the lines for part of the cycle and allows them to float for the
remainder of the cycle, parity errors are possible on the internal Model 743/744 's bus, resulting
in an HP-UX panic and system crash. In HP-UX, this parity error results in a non-zero value of
the bus check displayed as part of HP-UX panic. The HP-RT error message indicates that the
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