Getting Service Contact us should you require any service or assistance. SHANGHAI JYTEK Co., Ltd. Web site: http://www.jytek.com Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203 China Tel: +86-21-5047-5899 Fax: +86-21-5047-5899 Email: service@jytek.com Additional information, aids, and tips that help users perform tasks Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
1 Introduction The JYTEK PCIe-69814 is a 4-channel, 12-bit, 80MS/s PCI Express digitizer providing speedy, high quality data acquisition. Each of the four input channels supports up to 80MS/s sampling, with 12-bit resolution A/D converter. 40MHz bandwidth analog input with 50Ω...
Windows operating systems. The development environment may be VB, VB.NET, VC++, BCB, and Delphi, or any Windows programming language that allows calls to a DLL. The WD-DASK user and function reference manuals are on the JYTEK website (www.jytek.com).
All I/O connectors are SMB Snap-on type. Input Faceplate Label Remark Analog Analog Input Channel Analog Analog Analog Ext. Clock Input for external sample clock to digitizer Ext. Digital Trigger External digital trigger input, receiving trigger signal from external instrument and initiating acquisition Synced Digital SDI0...
• Anti-static wrist strap • Antistatic mat JYTEK PCIe-69814 DAQ modules are electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the antistatic mat.
2�2 Installing the Module 1. Turn off the computer. 2. Remove the top cover. 3. Select an available PCI express x4 slot and remove the bracket-retaining screw and the bracket cover. 4. Line up the PCI express digitizer with the PCI expresss lot on the back panel. Slowly push down on the top of the PCI express digitizer until its card-edge connector is resting on the slot receptacle.
3 Operations This chapter contains information regarding analog input, triggering and timing for the PCIe- 69814. 3.1 Functional Block Diagram Analog 12 Bit ADC Front-End FPGA Calibration CLK IN Clock Distribution TRG IN SDI0 Buffer SDI1 SDI2 3�2 Analog Input Channel 3.2.1 Analog Input Front-End Configuration Calibration Source...
3�2�2 Input Range and Data Format Data format of the PCIe-69814 is 2’s complement. The ADC data of PCIe-69814 is on the 12 MSB of the 16-bit A/D data. D2 to D0 is SDI2 to SDI0, with D3 disregarded. A/D data structure is as follows.
Using a high-level programming library for high speed DMA data acquisition, the sampling period and the number of conversions needs simply to be assigned into specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA.
3�2�4 Synchronous Digital Input The PCIe-69814 has three synchronous digital input channels, SDI0, SDI1 and SDI1. These three digital input lines can be sampled synchronously with the Timebase clock for mixed signal applications. Thus the data transfer can reach 80 Mbit/s when using internal 80 MS/s Timebase clock.
3.3.2 External Digital Trigger An external digital trigger is generated when a TTL rising edge or falling edge is detected at the SMB connector TRG IN on the front panel. As shown, trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, and the minimum pulse width 20 ns.
3�4 Trigger Modes Trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs. The following trigger mode descriptions are applied to analog input function. 3�4�1 Post Trigger Mode Post-trigger acquisition is applicable when data is to be collected after the trigger event, as shown.
3�4�3 Pre-Trigger Mode Collects data before the trigger event, starting once specified function calls are executed to begin the pre-trigger operation, and stopping when the trigger event occurs. If the trigger event occurs after the specified amount of data has been acquired, the system stores only data preceding the trigger event by a specified amount, as follows.
limitations on the spacing between trigger events in each mode. Trigger events arriving too close to the previous instance will be ignored by the digitizer. • In Post-Trigger mode, the minimum spacing between trigger events is N+1 • In Delayed-Trigger mode, the minimum spacing between trigger events is (N+D)+1, where D is the number of the delayed setting Figure 3-10: Re-Trigger Mode Acquisition...
3�5 Timebase CLK IN To ADC 80M Xtal Synthesizer Board SDI0 Figure 3-11: PCIe-69814 Clock Architecture 3.5.1 Internal Sampling Clock The PCIe-69814 internal 80MHz crystal oscillator acts as a sampling clock for ADC. 3.5.2 External Reference Clock (PCIe-69814P only) The PCIe-69814P’s onboard PLL module allows SDI0 to act as an external reference clock. Synthesizer input switches to the clock source at SMB connector SDI0, generating precisely 80MHz clock for ADC.
3�6 ADC Timing Control 3�6�1 Timebase Architecture 480MHz For ADC Onboard Multiplier ADC Output Data Bus 80MHz 80MHz Oscillator 80MHz For ADC State machine FPGA Figure 3-12: PCIe-69814 Timebase Architecture 3.6.2 Basic Acquisition Timing The PCIe-69814 commences acquisition upon receipt of a trigger event originating with software command, external digital trigger.
To achieve sampling rates other than 80MS/s, a number for scan interval counter needs only be specified. For example, if the scan interval counter is set as 2, the equivalent sampling rate is 80MS/s / 2 = 40MS/s. If as 3, the equivalent sampling rate is 80MS/s / 3 = 26.66MS/s, and vice versa.
3�7 Synchronizing Multiple Modules The PCIe-69814 provides a dedicated connector as system synchronization interface, enabling multiple module synchronization. As shown, bi-directional SSI I/Os provides a flexible connection between modules, allowing one SSI master PCIe-69814 to output SSI signals to other slave modules. For more accurate synchronization between modules, external sampling clock or external reference clock should be applied.
3�7�1 Card Number Configuration When multiple cards are used in a single chassis, card number configuration via switch, as shown. Figure 3-15: Card Number Configuration Switch When all sliders are in ON position, card number is 15, when all are OFF, card number is 0, as shown.
Slider 1 Slider 2 Slider 3 Slider 4 Card # Table 3-6: Card Number Configuration Settings Default card number is 15. 3�7�2 SSI_TRIG As an output, the SSI_TRIG signal reflects the trigger event signal in an acquisition sequence. As an input, the PCIe-69814 accepts the SSI_TRIG signal to be the trigger event source.
3�9 Multi-boot The PCIe-69814 supports software-based firmware updates. If firmware updates fail, the system may be unable to recognize the module, in which case the following steps may solve the problem. 1. Config SW2 to “on” 2. Install the module and restart the system 3.
The PCIe-69814 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PCIe-69814 driver loads these calibration constants, such that analog input path errors are minimized. JYTEK provides a software API for calibrating the PCIe-69814.
Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. • Read these safety instructions carefully. • Keep this user’s manual for future reference. •...
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