Subscribe to Our Youtube Channel
Related Manuals for JYTEK PCIe-69834
Summary of Contents for JYTEK PCIe-69834
- Page 1 PCIe-69834 4CH 16-bit 80MS/s Digitizer PCIe-69834/PCIe-69834P User’s Manual Manual Rev.: 2.00 Revision Date: June 3, 2016 Part No: 50-11263-1000...
- Page 2 Revision History Revision Release Date Description of Change(s) 2.00 June 3. 2016 Initial Release...
- Page 3 Environmental Responsibility JYTEK is committed to fulfill its social responsibility to global environmental preservation through compliance with the Euro- pean Union's Restriction of Hazardous Substances (RoHS) direc- tive and Waste Electrical and Electronic Equipment (WEEE) directive.
- Page 4 Additional information, aids, and tips that help users perform tasks. NOTE: NOTE: Information to prevent minor physical injury, component dam- age, data loss, and/or program corruption when trying to com- plete a task. CAUTION: Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.
-
Page 5: Table Of Contents
Table of Contents Preface ..................iii List of Figures ............... vii List of Tables................ix 1 Introduction ................ 1 Features................1 Applications ................. 2 Specifications............... 2 1.3.1 Analog Input ............... 2 1.3.2 Timebase..............4 1.3.3 Triggers ..............4 1.3.4 General Specifications..........5 Software Support .............. - Page 6 3.3.2 External Digital Trigger ..........17 3.3.3 Analog Trigger ............18 Trigger Modes..............18 3.4.1 Post Trigger Mode ............ 18 3.4.2 Delayed Trigger Mode ..........19 3.4.3 Pre-Trigger Mode............19 3.4.4 Middle Trigger Mode..........20 3.4.5 Acquisition with Re-Triggering ........20 Timebase ................21 3.5.1 Internal Sampling Clock...........
-
Page 7: List Of Figures
Figure 1-1: Analog Input Channel Bandwidth ....... 3 Figure 1-2: PCIe-69834 Schematic..........7 Figure 1-3: PCIe-69834 I/O Array ..........8 Figure 3-1: Analog Input Architecture ......... 13 Figure 3-2: Linked List of PCI Address DMA Descriptors ... 16 Figure 3-3: Trigger Architecture .......... - Page 8 This page intentionally left blank. viii List of Figures...
-
Page 9: List Of Tables
List of Tables Table 1-1: Channel Characteristics........... 3 Table 1-2: PCIe-69834 I/O Array Legend ......... 9 Table 3-1: Input Range and Data Format ........14 Table 3-2: Input Range FSR and –FSR Values......14 Table 3-3: Input Range Midscale Values ........15 Table 3-4: Counter Parameters and Description ...... - Page 10 This page intentionally left blank. List of Tables...
-
Page 11: Introduction
Introduction The JYTEK PCIe-69834 is a 4-channel, 16-bit, 80MS/s PCI Express digitizer providing speedy, high quality data acquisition. Each of the four input channels supports up to 80MS/s sampling, with16-bit resolution A/D converter. 40MHz bandwidth analog input with 50Ω impedance receives ±0.5V, ±1V, ±5V, and ±10V... -
Page 12: Applications
1.2 Applications Testing/monitoring for Energy Management applications, including: Partial discharge Power line/device monitoring Non-destructive testing Radar acquisition LiDAR 1.3 Specifications 1.3.1 Analog Input Item Spec Notes Channels 4 single-ended Connector type Input coupling 16-Bit resolution ±... -
Page 13: Figure 1-1: Analog Input Channel Bandwidth
Item Spec Notes Gain Error ±0.15% 0.1mV ±0.5V 0.15mV ±1V System Noise (RMS) ±5V 1.5 mV ±10 V -80 dB ±0.5 V Crosstalk -90 dB ±1 V or ± 5V or ± 10V 67 dB -78 dB SFDR 78 dB Table 1-1: Channel Characteristics CH0 50 Bandwidth... -
Page 14: Timebase
1.3.2 Timebase Sample Clock Detail Comment Internal : onboard crystal oscillator Timebase options External : CLK IN (front panel) Sampling clock 1.22kS/s to Internal : 80MHz frequency 80MS/s < ± External reference REF_CLK (supported by clock source PCI-69834P only) External reference clock External reference 3.3V to 5V TTL... -
Page 15: General Specifications
8.162 8.435 Power (W) 1.4 Software Support JYTEK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from pro-gramming libraries, such as DLLs, for most Windows-based sys-tems, JYTEK also provides drivers for other application environments . -
Page 16: Wd-Dask
All software options are included in the JYTEK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your JYTEK dealer to purchase the software license. -
Page 17: Device Layout And I/O Array
1.5 Device Layout and I/O Array All dimensions are in mm NOTE: NOTE: Figure 1-2: PCIe-69834 Schematic The PCIe-69834 I/O array is labeled to indicate connectivity, as shown. Introduction... -
Page 18: Figure 1-3: Pcie-69834 I/O Array
Figure 1-3: PCIe-69834 I/O Array All I/O connectors are SMB snap-on. Introduction... -
Page 19: Table 1-2: Pcie-69834 I/O Array Legend
(PCIe-69834P with PLL module only) REF_CLK can be used to receive Ext. Reference REF_CLK an external reference 10MHz clock Clock Input to generate ADC timebase. See Section 3.5.2 External Reference Clock (PCIe-69834P only) Table 1-2: PCIe-69834 I/O Array Legend Introduction... - Page 20 This page intentionally left blank. Introduction...
-
Page 21: Getting Started
Antistatic mat The JYTEK PCIe-69834 is electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti- static wristband, grounded at the same point as the anti-static mat. -
Page 22: Installing The Module
If any of these items are missing or damaged, contact the dealer Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing materials for inspection. Please contact your JYTEK dealer/ vendor immediately for assistance and obtain authorization before returning any product. -
Page 23: Operations
Operations This chapter contains information regarding analog input, trigger-ing and timing for the PCIe- 6 9834. 3.1 Functional Block Diagram Analog 16 Bit ADC Front-End FPGA Calibration CLK IN Clock Distribution REF_CLK TRIG IN 3.2 Analog Input Channel 3.2.1 Analog Input Front-End Configuration Calibration Source 16-bit ADC... -
Page 24: Input Range And Data Format
For auto-calibration, internal calibration provides stable and accurate reference voltage to the AI. 3.2.2 Input Range and Data Format Data format of the PCIe-69834 is 2’s complement. …. D15 to D0 bits represent the 16-bit data from ADC (2’s complement) -
Page 25: Dma Data Transfer
0.015 mV -0.015 mV Digital Code 0001 0000 FFFF Table 3-3: Input Range Midscale Values 3.2.3 DMA Data Transfer The PCIe-69834, a PCIe Gen 1 X 4 device, is equipped with 80MS/s high sampling rate ADC, generating MByte/second rate. To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve full potential PCI Express bus bandwidth. -
Page 26: Figure 3-2: Linked List Of Pci Address Dma Descriptors
the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of the system. Users can also link descriptor nodes circularly to achieve a multi- buffered DMA. -
Page 27: Trigger Source And Trigger Modes
(Master => Slave) (Master <= Slave) Figure 3-3: Trigger Architecture The PCIe-69834 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PCIe-69834 supports internal software trigger, external digital trigger, and analog trigger. -
Page 28: Analog Trigger
Post-trigger acquisition is applicable when data is to be collected after the trigger event, as shown. When the operation starts, PCIe-69834 waits for a trigger event. Once the trigger signal is received, acquisition begins. Data is generated from ADC and transferred to system memory continuously. -
Page 29: Delayed Trigger Mode
Figure 3-5: Post-Trigger Acquisition 3.4.2 Delayed Trigger Mode Delayed-trigger acquisition is utilized to postpone data collection after the trigger event, as shown. When the PCIe-69834 receives a trigger event, time delay implemented before commencing acquisition. The delay is specified by a 16-bit... -
Page 30: Middle Trigger Mode
Trigger Event Occurs Trigger signals occuring before the specified Operation start Acquisition stop amount of data has been acquired are ignored Acquisition start Data transfer to system begins Time Trigger Data N samples X samples have been acquired before trigger occurs, where X<N Figure 3-7: Pre-Trigger Mode Acquisition 3.4.4 Middle Trigger Mode... -
Page 31: Timebase
In Delayed-Trigger mode, the minimum spacing between trigger events is (N+D)+1, where D is the number of the delayed setting Figure 3-9: Re-Trigger Mode Acquisition 3.5 Timebase CLK IN To ADC 80M Xtal Synthesizer PLL Board REF_CLK Figure 3-10: PCIe-69834 Clock Architecture Operations... -
Page 32: Internal Sampling Clock
3.5.1 Internal Sampling Clock The PCIe-69834 internal 80MHz crystal oscillator acts as a sam-pling clock for ADC. 3.5.2 External Reference Clock (PCIe-69834P only) The onboard PLL module allows REF_CLK to act as an external reference clock input, such that when multi-card synchronization... -
Page 33: Adc Timing Control
Figure 3-11: Timebase Architecture 3.6.2 Basic Acquisition Timing The PCIe-69834 commences acquisition upon receipt of a trigger event originating with software command, external digital trigger. The Timebase is a clock provided to the ADC and acquisition engine for essential timing. The Timebase is from an onboard syn-thesizer. -
Page 34: Figure 3-12: Basic Digitizer Acquisition Timing
480MHz For ADC Onboard Multiplier ADC Output Data Bus 80MHz 80MHz Oscillator 80MHz For ADC State machine FPGA Figure 3-12: Basic Digitizer Acquisition Timing To achieve sampling rates other than 80MS/s, a number for scan interval counter needs only be specified. For example, if the scan interval counter is set as 2, the equivalent sampling rate is 80MS/s / 2 = 40MS/s. -
Page 35: Synchronizing Multiple Modules
Re-Triggering Table 3-4: Counter Parameters and Description 3.7 Synchronizing Multiple Modules The PCIe-69834 provides a dedicated connector as system syn- chronization interface, enabling multiple module synchronization. As shown, bi-directional SSI I/Os provides a flexible connection between modules, allowing one SSI master PCIe-69834 to output SSI trigger signals to other slave modules.For more accurate syn-... -
Page 36: Table 3-5: Ssi Signal Location And Pin Definition
The table summarizes SSI functionalities. Different signals cannot be routed onto the same trigger bus line. NOTE: NOTE: SSI Timing Signal Function SSI Trig Input/output trigger signal through SSI All SSI signals are routed to the 16-pin connector from FPGA, enabling multi-module synchronization. -
Page 37: Figure 3-14: Card Number Configuration Switch
Figure 3-14: Card Number Configuration Switch When all sliders are in ON position, card number is 15, when all are OFF, card number is 0, as shown. Slider 1 Slider 2 Slider 3 Slider 4 Card # Operations... -
Page 38: Ssi_Trig
SSI_TRIG As an output, the SSI_TRIG signal reflects the trigger event signal in an acquisition sequence. As an input, the PCIe-69834 accepts the SSI_TRIG signal to be the trigger event source. The signal is configured in the rising edge-detection mode. -
Page 39: Measurement Function Api
Figure 3-15: Flash Memory Configuration Switch 3.9 Measurement Function API The PCIe-69834 supports measurement function APIs for easily conversion of basic voltage/time measurement results, with no extra programming required for development of scoping applica-tion software. Operations... -
Page 40: Figure 3-16: Waveform Transition
Overshoot High Reference Level Amplitude Low Reference Level Preshoot Transition Time Figure 3-16: Waveform Transition Parameter Descr. Comments Type Unit Highest Refer to Figure 3-16, Double V waveform value “Waveform Transition” Lowest Refer to Figure 3-16, Double V waveform value “Waveform Transition”... - Page 41 Parameter Descr. Comments Type Unit Duration of one complete waveform cycle, calculated in WD-DASK via period Double Sec the interval between first and third mid reference level crossings Reciprocal of freq 1 / period Double Hz period Negative pulse width, the duration between two negwidth...
- Page 42 Parameter Descr. Comments Type Unit Duration of signal falling Refer to Figure 3-16, falltime Double Sec from high to low “Waveform Transition” reference level Voltage high, calculated via histogram, using the voltage of the histogram bin with the wd_hist high high->value maximum _bin...
-
Page 43: Table 3-7: Measurement Parameters
Parameter Descr. Comments Type Unit Peak distortion following a valid ((local max – voltage high)/ posovershoot Double positive amplitude)*100% transition Peak distortion preceding a ((local max – voltage high)/ negpreshoot Double valid negative amplitude)*100% transition Peak distortion following a valid ((voltage low –... - Page 44 This page intentionally left blank. Operations...
-
Page 45: A Appendix: Calibration
EEPROM. At system boot, the PCIe-69834 driver loads these calibration con-stants, such that analog input path errors are minimized. JYTEK provides a software API for calibrating the PCIe-69834. The onboard EEPROM provides two banks for calibration con- stant storage. -
Page 46: Figure A-1: Auto-Calibration Block Diagram
Before initializing auto-calibration, it is recommended to warm up PCIe-69834 least minutes remove connected cables. It is not necessary to manually factor delay into applications, as the PCIe-69834 driver automatically adds the compensation time. NOTE: NOTE: PCIe-69834 Onboard Calibration Source Switch... -
Page 47: Figure A-2: Auto-Calibration Flow
Auto-calibration start Set analog front end input Set calibration source to onboard calibration source to calibration voltage Set calibration source Capture data and calculate to ground gain compensation parameters Capture data and calculate Are all channels and offset compensation parameters all ranges complete? Are all channels and all ranges complete? - Page 48 This page intentionally left blank. Calibration...
-
Page 49: Important Safety Instructions
Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this user’s manual for future reference. ... - Page 50 Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. Risk of explosion if battery is replaced with an incorrect type; please dispose of used batteries appropriately. Equipment must be serviced by authorized technicians ...
Need help?
Do you have a question about the PCIe-69834 and is the answer not in the manual?
Questions and answers