Matrox Rapixo CXP Installation And Hardware Reference page 9

24 V
Opto Aux I (2) n
LVDS Aux In (2)
LVDS Aux Out (1)
TTL Aux I/Os (3)
Opto Aux I (2) n
LVDS Aux In (2)
LVDS Aux Out (1)
TTL Aux I/Os (3)
Opto Aux I (2) n
LVDS Aux In (2)
LVDS Aux Out (1)
TTL Aux I/Os (3)
Opto Aux I (2) n
LVDS Aux In (2)
LVDS Aux Out (1)
TTL Aux I/Os (3)
* Note that this block represents only the customizable processing block of the on-board
FPGA. Other functionality in this diagram is also implemented using the FPGA.
I/O data / Image data
Power-over
12 V
Internal auxiliary 12 V
Coa XP ress
power connector
24V
12.5 Gbits/s
Coa XP ress
interface
41.66 Mbits/s
Coa XP ress
interface
Coa XP ress
interface
Coa XP ress
interface
Auxiliary I/O
interface
Auxiliary I/O
interface
Auxiliary I/O
interface
Auxiliary I/O
interface
LUTs
GPIO
controller
MIL License
Fingerprint
and
supplemental
MIL license
storage
Matrox Rapixo CXP board
Matrox Rapixo CXP Pro
On-board memory
( DDR SDRAM 4 )
8 GB
38.4 GB /s
Processing FPGA
(customizable block)*
16/32
Memory GB/s
Processing
Controller
Units
8 GB /s
8 GB /s
Host Interface
Color space
converter &
pixel formatter
Bayer decoder
DMA Read
DMA Write
8 GB /s
full duplex
Host x8 PCI e 3.1 bus
9