Seagate
F3 architecture
100110101010110011010101011001101010101100110101010110011010101011001101010101100110101010110011010101011011010101011
10101010110011010101011011010101001101010100110101101101101010100101
1011010101100110011010101011010101111010111
11010101101101010100111110
1101110110110011
0111011110
111101
011
11
1
DT can be accessed 'By table' - from the list of scanned (during start or from the utility status dialog) DT or directly by
their identifiers – 'By ID'. In the latter case you have to select additionally the DT source: ROM or RAM.
The RAM tab provides access to the objects in the random-access memory of the controller.
The following parts of address space are distinguished at that:
♦
Controller memory (general memory)
♦
DRAM (controller memory array)
♦
Servo Data (servo program address space)
♦
Servo Program (servo program address space)
42
01010101100110101010110011010101011001101010101100110101010110011010101011001101010101100110
Fig. 7.3
Fig. 7.4
PC-3000 EXPRESS / UDMA / PORTABLE
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