ACE Lab PC-3000 Express Manual page 42

Seagate f3 architecture
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Seagate
F3 architecture
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DT can be accessed 'By table' - from the list of scanned (during start or from the utility status dialog) DT or directly by
their identifiers – 'By ID'. In the latter case you have to select additionally the DT source: ROM or RAM.
The RAM tab provides access to the objects in the random-access memory of the controller.
The following parts of address space are distinguished at that:
Controller memory (general memory)
DRAM (controller memory array)
Servo Data (servo program address space)
Servo Program (servo program address space)
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Fig. 7.3
Fig. 7.4
PC-3000 EXPRESS / UDMA / PORTABLE 
Technical support: ts@acelab.ru
Phone: +7 863 201 50 06
ts.acelaboratory.com
 ACE Lab

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