Toshiba Satellite L730 Maintenance Manual page 82

This subtest first writes data patterns and address data from 32MB to the
maximum installed memory, reads the new data, and then compares the result
with the original data patterns. Addresses are displayed in 64KB increments
during the test.
Test Process:
1. Byte Enable Test
2. Byte Enable Test
3. Data bus test
4. Fixed data test
5. Address pattern test
Subtest 04 RAM Refresh
This subtest writes a data pattern (CCAA5533H ) in 4KB from 0 to the
maximum installed memory, then waits for a memory refresh cycle (16 ms or
more), reads the new data, and compares the result with the original data
pattern.
20
One bit write/ 8 bit read" is executed and the new data is compared
with the original data.
Test data = CCAA5533H, 80000000H
"One bit write/16 bit read" is executed and the new data is compared
with the original data.
Test data = CCAA5533H, 80000000H
"One bit write/16 bit read" is executed and the new data is compared
with the original data.
Test data = 1H, 2H, 4H, 8H, 10H, through 80000000H.
"16 bit write/ 16 bit read" is executed and the new data is compared
to the original data.
Test data = FFFFFFFFH, 00000000H, 80018001H
"16 bit write and 16 bit read" of address pattern data is executed and
the new data is compared with the original data.
Test data = 0000H, 0004H, 0008H, 000CH,...8000H, 8004H, through
FFECH
Test Program for Field.
Satellite L730 Tests and Diagnostics Manual