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Setup
PIN
SIGNAL
1
V48_X
3
V12_X
5
ENABLE_S
7
CH1_S
9
DIR
11
ISETA
13
ISETD
15
SYNCIN_S
17
SYNCOUT_S
19
OPT
21
CH2_S
23
+3.3 V
25
+5 V
27
IOUT1_S
29
IOUT2_S
31
IOUT1_X
33
IOUT2_X
35
AGND
37
PGND
39
DT_S
41
DT_X
43
+10 V
45
nFAULT_X
47
UVLO_X
49
CH1_X
51
CH2_X
53
SYNCIN_X
55
SYNCOUT_X
57
nFAULT_X
59
KEY
All even
AGND
number pins
(1)
J18 is the interface connector to the slave EVM in the multiphase configuration if the host EVM serves as the master. All control
commands and control signals are sent through J18 to the slave EVM's J17.
(2)
I = input pin
(3)
O = output pin
10
LM5170-Q1 EVM User Guide
Table 5. J18 60-Pin Header Description
I/O
DESCRIPTION
—
No Connect
—
No Connect
(2)
I
Slave EVM enable (connect to the UVLO pin of the slave IC)
I
Slave EVM CH-1 control (connect to the EN1 pin of the IC)
I
Direction command
I
Channel current setting (analog voltage)
I
Channel current setting (PWM signal)
I
The external clock input for the slave
(3)
O
Slave EVM clock output signal
I
Interleave angle setting
I
Slave EVM CH-2 control (connect to the EN1 pin of the IC)
I
Output of onboard +3.3-V voltage
I
Output of onboard +5-V voltage
O
Slave EVM CH-1 monitor in 3 or 4 phases
O
Slave EVM CH-2 current monitor in 3 or 4 phases
—
Not used
—
Not used
I/O
Reference GND for control signals
O
Power ground of the DC-DC converter
I
Slave EVM dead time adjustment pin
—
No Connect
I
Input of +10-V bias supply, or output of onboard +10-V bias supply
I/O
Slave EVM fault report flag, or external shutdown command pin
—
No Connect
—
No Connect
—
No Connect
—
No Connect
—
No Connect
—
No Connect
—
No Connect
I/O
All signals' return
Copyright © 2016, Texas Instruments Incorporated
(1)
SNVU543A – November 2016 – Revised December 2016
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