Console Odt Mode - Digital Equipment Micro PDP-11/53 Supplement Manual

DIAGNOSTICS
Line 3 -- Has the following four parts.
1. A short description of the failed area:
JII
JIl FP
JIl MMU
J1I nnn
LTC CSR
SLUO
SLUI
ROM
RAM
RAM CSR
Q-Bus RAM
Q-Bus CSR
JII test error
floating point test error
memory management test error
unexpected trap to virtual address nnn
line time clock test error
console SLU test error
second SLU test error
ROM checksum test error
onboard memory test error
onboard memory parity test error
Q-Bus memory test error
Q-Bus memory parity test error
All areas except Q-Bus RAM and Q-Bus CSR are on the KDJII-DA
module.
2. The virtual PC of the failure -- generally useful only with a
program listing
3. The physical address of the failure -- generally useful only
with a program listing
4. Only displayed with RAM errors, this part displays:
address/found data <> expected data
(the failing location, the bad data, and the expected data)
6.3 CONSOLE ODT MODE
Console ODT mode is entered in one of the following ways.
• The operator pressing the console terminal <BREAK> key, if
halt-on-break jumper WII (on the CPU module) is not installed,
or the halt-on-break switch is not disabled (on the console
display panel printed circuit board).
NOTE
The break key must be enabled on the terminal also. For example,
on a VT220 the break key can be disabled.
• Execution of a Halt instruction in kernel mode, if halt option
jumper WI (on the CPU module) is installed.
• Q22-Bus BHALT line is asserted on the backplane.
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