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Winbond W90P710 Programming Manual

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NO:
VERSION:
PAGE:
W90P710 Programming Guide
2.1
1
W90P710 Programming Guide
Revision 2.1
01/06/2006
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A

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  • Page 1 VERSION: PAGE: W90P710 Programming Guide W90P710 Programming Guide Revision 2.1 01/06/2006 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 2 Initial Version for W90P710 Major Revision 01/06/2006 Modify some contents and re-order the sections The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 3: Table Of Contents

    SDRAM interface......................26 Registers ..........................27 Functional Descriptions ......................27 2.4.1 EBI Control Register (EBICON)..................27 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 4 GDMA ............................58 Overview..........................58 Block Diagram ........................59 Registers ..........................60 Functional Descriptions ......................60 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 5 Register Map ........................95 Functional descriptions ......................97 7.4.1 Initialization........................97 7.4.2 Endpoint Configuration ....................98 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 6 Configure how to show image on the panel ................ 124 9.12 Enable FIFO ........................125 9.13 Enable LCD Controller......................126 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 7 Timer Interrupt Service Routine................... 159 12.4.4 Watchdog Timer ......................160 AIC (Advanced Interrupt Controller) ..................163 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 8 Overview..........................191 16.2 Registers ..........................191 16.3 Functional Description ......................193 16.3.1 Initialization Sequence....................193 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 9 PWM Timer Stop Procedure..................220 Keypad Interface ........................222 20.1 Overview..........................222 20.2 Block Diagram ........................223 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 10 Read scan code and ASCII code................. 231 21.4.4 Interrupt Service Routine ..................... 232 21.4.5 Example........................235 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 11 Figure 10-1 Block diagram of Audio Controlle................... 129 Figure 10-2 AC97 Playback Data in DMA Buffer ................135 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 12 Figure 19-5 PWM Timer Stop flow chart (method 2)................. 221 Figure 20-1 Keypad Controller Block Diagram.................. 223 Figure 20-2 KPI Interface flowchart....................225 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 13 Figure 21-2 Key map of extended keyboard & Numeric keypad ............228 Figure 21-3 Make Code and Break Code..................229 Figure 21-4 Example ISR........................233 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 14 Table 21-4 Register PS2ASCII ......................232 Table 21-5 Register PS2ST ......................232 Table 21-6 LED Status byte ......................235 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 15: Overview

    Ethernet controller that reduces total system cost. A color LCD controller is built in to support black-and- white/gray-level/color TFT and low cost STN LCD modules. Most of the on-chip function blocks have been designed using an HDL synthesizer and the W90P710 has been fully verified in Winbond’s state- of-the art ASIC test environment.

  • Page 16: Figure 1-1 W90P710 Functional Block Diagram

    Chapter 5. GDMA • Chapter 6. USB Host Controller • Chapter 7. USB Device Controller The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 17 Chapter 19. PWM-Tmer • Chapter 20. Keypad Interface • Chapter 21. PS/2 Host Interface Controller The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 18: Features

    • Full compliance with IEEE standard 802.3 • RMII interface only • Station Management Signaling The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 19: Dma Controller

    • Supports DMA function to accelerate the data transfer between the internal buffer, external SDRAM, and flash memory card The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 20: Lcd Controller

    Color-look up table size 256x32 bit for TFT used Dedicated DMA for block transfer mode The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 21: Channel Ac97/I2S Audio Codec Host Interface

    • Automatically clear the interrupt flag when the interrupt source is programmed to be edge- triggered The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 22: Gpio

    • Parity error counter in reception mode and in transmission mode with automatic re-transmission • Automatic activation deactivation sequence through an independence sequencer The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 23: I2C Master

    • Programmable duty control of output waveform (PWM) • Auto reload mode or one-shot pulse mode • Dead zone generator The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 24: Keypad Interface

    • Power-Down mode to stop all clocks included external crystal oscillator. • Exit IDLE/Power-Down by interrupts • The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 25: Ebi (External Bus Interface)

    The EBI also offer power-on setting to ensure the system can be boot by from ROM/FLASH. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 26: Block Diagram

    DQM[3:0] SDRAM W90P710 64Mb 512Kx4x32 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 27: Registers

    CLKEN and REFEN can be disabled to reduce save power consumption. Another way to save reduce power consumption is just to disabling CLKEN, and The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 28: Rom/Flash Control Register

    RESERVED memory address. The system memory map can be found in W90P710 spec data sheet. After system reset, the EBI controller has uses the special power-on setting to ensure the boot ROM to be bootable.

  • Page 29: Sdram Configuration Registers

    SDRAM controller. There are two configuration registers SDCONF0, SDCONF1 for SDRAM bank 0, bank 1 respectively. Each bank can have been set to different configurations. W90P710 also offers the flexible timing control registers to control the generation and processing of the control signal and can suit to control the timing of different speed type of SDRAMs.

  • Page 30: External I/O Control Registers

    SDRAM when for each access. 2.4.4 External I/O control registers The W90P710 supports an external device control without glue logic. It is very cost effective because provides address decoding and control signals timing logic are not needed. The control registers can control special external I/O devices for providing the low cost external devices control solution.
  • Page 31 FLASH/ROM. After the system initialization the memory map becomes the After Initialization of Figure 2-4. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 32: Remapping

    In W90P710 the memory remapping can be achieved by setting EBI control registers. The following example is a MACRO, which achieves performs the remapping when booting. The program flow of this example is as Figure 2-4.
  • Page 33 ; The value of current pc is the run-time address of “$label.temp” r1, pc LDR r3, =$label.EndSysMapJump The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 34 DCD rSDCONF1; base=0x2000000,size=32MB,MRSET=1,AUTOPR=1,LATENCY=3MCLK, ; LENGTH=1Byte,COMPBK=2bank,DBWD=32bit,COLUM=8bit DCD rSDTIME0 ; tRCD=8MCLK,tRDL=4MCLK,tRP=8MCLK,tRAS=8MCLK DCD rSDTIME1 ; tRCD=8MCLK,tRDL=4MCLK,tRP=8MCLK,tRAS=8MCLK ALIGN MEND The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 35: Cache Controller

    3 Cache Controller 3.1 Overview The W90P710 incorporates a 4KB Instruction cache, a 4KB Data cache, and 8 words write buffer to improve the system performance. The caches consist of high-speed SRAM that provides quicker access time than external memory. If cache is enabled, the CPU tries to fetch instructions from I- cache instead of external memory.

  • Page 36: Block Diagram

    4 words cache line 4 words cache line Set0 Set1 7-bit Set127 32-bit 32-bit Way Select 32-bit The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 37: Figure 3-2 Data Cache Organization Block Diagram

    4 words cache line 4 words cache line Set0 Set1 7-bit Set127 32-bit 32-bit Way Select 32-bit The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 38: Registers

    Table 3-1 The size and start address of On-Chip RAM ICAEN DCAEN On-Chip RAM Size Start Address 0x7FE0.0000 0x7FE0.0000 0x7FE0.1000 Unavailable The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 39: Non-Cacheable Area

    Address Register (CAHADR) must be set before flush a single cache line. Due to W90P710 does not support external memory snooping; it is necessary to flush cache if the force consistency of cache and memory is required. For example, The I-Cache should be flushed after a self-modifying code is executed.

  • Page 40: Cache Load And Lock

    ? There are some limitations during the locking cache line into the I-Cache or D-Cache. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 41: Cache Unlock

    To unlock the whole instruction cache, set the ULKA and ICAH bits. To unlock the whole data cache, set the ULKA and DCAH bits. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 42: Emc (Ethernet Mac Controller)

    • Supports internal loop back mode for diagnostic. • Supports 256 bytes embedded transmit and receive FIFO. • Supports DMA function. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 43: Block Diagram

    MII Management (RxMAC, TxMAC) State Machine MDIO TX_CLK RMII2MII Domain Station Management Interface RMII Interface The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 44: Registers

    Receive Descriptor Link List Start Address 0xFFFF.FFFC RXDLSA Register 0xFFF0.3090 MAC Command Register 0x0000.0000 MCMDR The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 45: Emc Status Registers

    (5) Set start address of next descriptor, this field of the last descriptor should set to the address of the first descriptor. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 46 (6) The start address of descriptor and data buffer are suggested to be aligned to 16 bytes address boundary. Figure 4-2 lists the Rx Descriptor initialization flow. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 47: Figure 4-2 Rx Descriptor Initialization

    The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 48: Initialize Tx Buffer Descriptors

    (7) The start address of descriptor and data buffer are suggested to be 16 bytes alignment. Figure 4-3 lists the Tx Descriptor initialization flow. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 49: Figure 4-3 Tx Descriptor Initialization

    Set I, C, P bits of each descriptor(These bits also can be set before transmit packets) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 50: Mii

    100BASE-T4 capable 100BASE-TX full duplex capable 100BASE-TX half duplex capable 10BASE-T full duplex capable The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 51 (3) Read status register #2 to get speed and operation mode that is the result of auto- negotiation. (4) Set speed and operation mode of MAC The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 52: Control Frames

    (8) Set TXON bit of MCMDR register if it is not set. (9) Write TSDR register. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 53: Figure 4-4 Packet Transmission Flow

    Set TXON bit of MCMDR register if it didn't be set Write TSDR register MAC Processing The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 54 (5) Set the next descriptor to Tx software pointer. (6) Transmit the next packet if there is packet available in device queue. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 55: Figure 4-5 Tx Interrupt Service Routine Flow

    Transmit the next packet if there is any packet available in the device queue End of Tx ISR The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 56 (7) Re-start from step (3) if descriptor of Rx software pointer is not the same as the one of CRXDSA register. (8) Write RSDR register. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 57: Figure 4-6 Rx Interrupt Service Routine

    Update the Rx S/W descriptor pointer to next descriptor Rx S/W Descriptor pointer the same as CRXDSA Write RSDR Exit Rx ISR The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 58: Gdma

    GDMA can be fixed also. Furthermore, the GDMA supports 4-data burst mode to boost performance and supports demand mode to speed up external GDMA operations. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 59: Block Diagram

    GDMA nDACK nDACK Interface nDREQ nDREQ nXDACK SWREQ 0 SWREQ 1 nXDREQ GDMA block The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 60: Registers

    (GDMA_CTL). It is used to control the transfer behavior of the GDMA operation, such as the transfer mode, transfer count, transfer width and interrupt mask. Figure 5-2 lists the content of GDMA_CTL. The detail description of each bit-field can be found in W90P710 data sheet.

  • Page 61: Figure 5-2 The Bit-Fields Of The Gdma Control Register

    (GDMA_TCNT). The GDMA operation is continued until the transfer count register is counted down to zero. Figure 5-3 shows the programming flow for GDMA operation. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 62: Transfer Count

    16 * 2 = 32. But if the burst mode is enabled, the above equation will be changed as below. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 63: Transfer Termination

    GDMA didn’t complete this transfer, it will cause the GDMA transfer error bit to be set, and the The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 64: Figure 5-4 Software Gdma Transfer

    ( ! ( * ( ( v o l a t i l e U I N T * ) G D M A _ C T L 0 ) & 0 x 4 0 0 0 0 ) ) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 65: Gdma Operation Started By Nxdreq

    • The GDMA is operated in external nXDREQ mode (GDMANS=01b). • Single mode is valid. • Demand mode is valid. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 66: Fixed Address

    When bit DM of register GDML_CTL is set to 1, GDMA controller transfers data as long as the signal nXDREQ is active. The amount of data transferred depends on how long the nXDREQ is active. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 67 (for example, in a DRAM refresh operation). The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 68: Usb Host Controller

    • List Management • Root Hub Management • Multiple low power modes for efficient power management The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 69: Registers Map

    Control and Status, Memory Pointer, Frame Counter and Root Hub. All of the registers should be read and written as Dwords. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 70: Block Diagram

    Master Interrupts Data Buffer USB Interface Clock Gen. Root Control Port1 Port2 AHB Master The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 71: Data Structures

    Except direct access to Host Controller by registers, Host Controller Driver must maintain the following memory blocks to communicate with Host Controller : • Endpoint Descriptor Lists The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 72: Endpoint Descriptor (Ed) Lists

    Specification 1.0a. In this document, you can find detail descriptions about each field in Endpoint Descriptor. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 73: Transfer Descriptor

    Host Controller to define a buffer of data that will be moved to or from an endpoint. Transfer Descriptors are linked to queues attached to EDs. The ED provides the endpoint address The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 74: Figure 6-2 General Transfer Descriptor Format

    TDs for the SETUP stage, DATA stage, and STATUS stage transfers. The TDs must be linked The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 75: Host Controller Communication Area

    OpenHCI Specification 1.0a. Detail descriptions about each field in HCCA can be found in this document. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 76: Programming Note

    ControlListEnable, and BulkListEnable bits of HcControl register 9. Let transit state writing Host Controller USBOPERATIONAL HostControllerFunctionalState field of HcControl register The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 77: Usb States

    You can find possible transitions of USB states in Table 6-3. The followings are some notes about the USB state transitions : The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 78: Add/Remove Endpoint Descriptors

    Bulk ED lists are referred to by HcControlHeadED register and HcBulkHeadED register respectively. The Interrupt endpoints are organized into 32 Interrupt ED lists with each list pointed by The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 79: Figure 6-4 Remove An Endpoint Descriptor

    SOF interrupt. In the next the SOF interrupt, HCD can guarantee that the ED list is not processed by Host Controller. Figure 6-4 Remove an Endpoint Descriptor The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 80: Add/Remove Transfer Descriptors

    4. Let TailP of ED point to the new dummy TD Figure 6-5 ED list and TD queue The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 81 NextTD field of the retired TD, and then have the HcDoneHead point to the retired TD In some situation, the client software may cancel an IRP before the IRP was completed. This The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 82: Irp Processing

    STATUS stage, which has DATA1 toggle setting. It must contain a zero bytes buffer. The following is an example code of Control Transfer : The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 83 Software should not deliver an IRP with transfer length exceeding 64 bytes. HCD makes only one TD for an Interrupt Transfer, which is one-shot. On completion of the TD, HCD may re-submit the The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 84: Interrupt Processing

    W90P710 USB Host Controller may raise the following interrupts : • SchedulingOverrun • WritebackDoneHead • StartOfFrame • ResumeDetected The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 85 StartOfFrame interrupt, HCD can ensure that the endpoint is not currently processed by Host Controller, and it can remove the TD. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 86 PortSuspendStatusChange, PortResetStatusChange bit of HcRhPortStatus[1/2] set, the Host Controller would raise the RootHubStatusChange interrupt. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 87 &regs->HcInterruptEnable); if (ints & OHCI_INTR_SO) USB_printf("Error! - USB Schedule overrun, count : %d\n", The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 88: Done Queue Processing

    HCD must reverse the Done Queue before it can start to process the retired TDs. The following is an example routine of reversing Done Queue : static TD_T *dl_reverse_done_list(OHCI_T * ohci) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 89 = td_list; td_list_hc = (UINT32)(td_list->hwNextTD) & 0xfffffff0; /* end of while */ return td_list; The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 90: Root Hub

    Root Hub. The HcRhPortStatus register presents the current status and reflects the change of status of a Root Hub port. W90P710 Root Hub has two hub ports, the HcRhPortStatus[1] and HcRhPortStatus[2] are respectively dedicated to port 0 and port 1.
  • Page 91 Some status bits are implemented with special write behavior. You can do the following actions to control the Root Hub port : The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 92 Root Hub appear as a normal hub device seems be a better solution. To accomplish this, HCD must The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 93 So, in the previous program segment, the requests to the Root Hub must be intercepted and forwarded them to the dedicated routine rh_submit_urb( ). The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 94: Usb Device Controller

    It also supports to detect the class and vendor requests. For GetDescriptor request and Class or Vendor command, the firmware will control these procedures. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 95: Block Diagram

    USB control transfer-out port 2 register 0x0000.0000 USB_ODATA3 0xFFF0.6024 USB control transfer-out port 3 register 0x0000.0000 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 96 USB endpoint C remain transfer length register 0x0000.0000 EPC_PKT 0xFFF0.60B0 USB endpoint C remain packet length register 0x0000.0000 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 97: Functional Descriptions

    12. After finished the above steps, set the USB_EN bit of USB_CTL to enable USB engine. The The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 98: Endpoint Configuration

    USB_IE or EPx_IE register is enabled. After service an interrupt, ISR has to set the relative bit of that interrupt in register USB_IC or EPx_IC to clear the interrupt status. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 99: Endpoint 0 Operation

    ISR handling endpoint 0 operations. The next section will describe how to respond the Get Device Descriptor standard request. Figure 10-2 USBD Controller Block Diagram The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 100: Get Descriptor

    If the host sends the standard request to get Device descriptor, the programmer could follow the steps below. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 101: Endpoint A ~ C Operation

    Polling EPx_RDY of register EPx_CTL until it is cleared or wait for EPx_DMA_IS interrupt in register EPx_IS. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 102: Example

    After the above steps, the host can appreciate a removable drive plug-in. And the user can access it using Windows File explorer. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 103: Sdio Host Controller

    DMA transfer between flash memory card and system memory. 8.2 Block Diagram Figure 8-1 SDIO Host Block Diagram The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 104: Registers

    0x FFF0.7010 SD Interrupt Status Register 0x0000.0000 SDBIST 0x FFF0.7014 SD BIST Register 0x0000.0000 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 105: Sdio Host Controller

    3. Set the ERRIEN, DRdIEN, DWrIEN, SDHIEN, and SDIOEN bits of SDIOIER register to enable all interrupts. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 106: Move Data From Sdram To Sdio Host Controller Buffer

    3. Set CO_EN bit of SDCR register to enable command output. 4. Polling CO_EN bit of SDCR register until it was cleared The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 107: Get Response From Sd/Mmc Card

    5. Polling DO_EN bit of SDICR register until it was cleared, or waiting for DO_IS interrupt bit of SDISR register 6. Check the CRC bit of SDIISR register The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 108: Lcd Controller

    The LCD Controller Block Diagram was shown in the Figure 9-1: Figure 9-1 LCD Controller Block Diagram The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 109 VERSION: PAGE: W90P710 Programming Guide The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 110: Table 9-1 Lcd Controller Register Map

    0xFFF0.80A0 OSD Window Ending Coordinate Register 0000.0000 OSDOVCN 0xFFF0.80A4 OSD Overlay Control Register 0000.0000 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...
  • Page 111 LCD SRAM Build In Self Test Register 0000.0000 Look Up Table SRAM 0xFFF0.8100 … 0xFFF0.84FF The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 112: Programming Procedure

    The overall programming flows are as Figure 9-2 and 9-3. Figure 9-2 Overall programming flow for LCD controller - 1 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 113 (OSDUPSCF , VDUPSCF , ( OSDOVCN , OSDKYP , OSDNSCF , VDDNSCF ) OSDKYM ) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 114: Figure 9-3 Overall Programming Flow For Lcd Controller - 2

    OSDWINE ) Change configuration ? Is FIFO disabled ? Enable FIFO ( FIFOCON ) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 1200-0003-07-A...

  • Page 115: Initialization

    1 = Enable VSYNC, HSYNC, VCLK, VD, and VDEN [13:12] YUV output sequence( only 00 = UYVY The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 116 5) Go to Step 9. 6) If external panel is TV, configure TV-related bits (LCDCON [7] and LCDCON [13:12]). The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 117: Configure Lcd Interrupt

    The relationship between screen, valid window, and OSD window is as Figure 9-4. Figure 9-4 The relationship between screen, valid window, and OSD window The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 118: Table 9-3 Osd Display Condition

    The Color-Key value indicates the color-key condition match or un-match. The OSD color-key pattern is defined in register OSDKYP for RGB components according to the source color The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 119: Configure Tft Palette Look-Up Table

    2) Fill color data into those addressable entries of LUT (address from 0xFFF0_8100 to 0xFFF0_84FF). The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 120: Configure Gray Level Dithered Data Duty Pattern

    Up-scaling function supports enlarging 2 or 4 times in vertical direction and 2 or 4 times in The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 121: Configure The Starting Address And The Stride Of Frame Buffer And Fifo

    When FIFO received the number of data which FIFOCOLCNT specified, VLINEFINSH interrupt is generated and The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 122: Figure 9-5 An Example To Explain How To Program The Starting Address And Stride

    FIFO1SADDR. Figure 9-5 An example to explain how to program the starting address and stride The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 123 LCD Panel, the setting of register is: FIFO1SADDR = 0x30000000 FIFO1COLCNT = 0x01E0 FIFO1ROWCNT = 0x01E0 FIFO1REALCOLCNT = 0x01E0 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 124: Configure How To Show Image On The Panel

    LCD can only show some portion of a whole image with cropping window and valid window provided by the controller. The programming procedure is as follows: The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 125: Enable Fifo

    Pixel 4 0008H Pixel 5 Pixel 6 ………. (2) 8bpp Display Table 9-8 BSWP=0, HSWP=0 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 126: Enable Lcd Controller

    1) Some interrupts occur and enter ISR. 2) Check which interrupts occur through interrupts status register (LCDINTS [18:16] and The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 127 3) Set the flags and clear the occurred interrupts (LCDINTC [18:16] and LCDINTC [5:0]). 4) Return to normal routine. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 128: Audio Controller

    An AHB master port and an AHB slave port are offered in audio controller. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 129: Block Diagram

    Record RFIFO PFIFO PLAY Control FIFO Control Controller Control FIFO Register AC-LINK Audio Interface The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 130: Registers

    DMA transfer. These facilities greatly reduce the loading of software. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 131: Table 10-1 Ac97 Output Frame

    For input and output direction, each AC-link frame contains a Tag slot and 12 data slots. However, in the 12 data slots, only 4 slots are used in W90P710, other 8 slots are not supported, and the control data and audio data are transferred in the 4 valid slots. Each slot contains 20 bits data.

  • Page 132: Cold Reset External Ac97 Codec

    Set VALID_FRAME and SLOT_VALID[0] bits of ACTL_ACOS0 register. The register index will be delivered by slot1 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 133 _debug_msg("ac97_read_register - R_INDEX of REG_ACTL_ACIS1 not match!, 0x%x\n", readw(REG_ACTL_ACIS1)); Delay(100); return (readw(REG_ACTL_ACIS2) & 0xFFFF); The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 134: Write Ac97 Registers

    Delay(100); /* polling the AC_W_FINISH */ for (nWait = 0; nWait < 0x10000; nWait++) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 135: Ac97 Playback

    … To playback PCM data to external AC97 codec, please follow the steps below: The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 136 After all PCM data has been played, clear the AC_PLAY bit of ACTL_RESET register to stop playback The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 137: Ac97 Record

    And pull AC_RESET bit of ACTL_RESET register high for 10ms to reset W90P710 AC97 interface. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 138: I2S Interface

    W90P710 audio controller provides DMA function for transferring PCM data from main memory to external I2S codec. It supports single-channel or 2 channels transfer. It should set base and address The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 139: Figure 10-4 I2S Play Data In Dma Buffer

    L3 interface. One is IIS compatible format; another is MSB- justified format. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 140: I2S Record

    FIFO, DMA_EN to enable DMA, the BLOCK_EN[0] to enable IIS interface, and AUDIO_EN to enable the audio controller. These bits are all in the register ACTL_CON. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 141 7. Set the register ACTL_RESET to set channel and start to record. Then play the sound, which record before and verify it. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 142: Uart

    Transmit Holding Register (DLAB = 0) Undefined UART0_IER 0xFFF8.0004 Interrupt Enable Register (DLAB = 0) 0x0000.0000 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 143 UART2_FCR 0xFFF8.0208 FIFO Control Register Undefined UART2_LCR 0xFFF8.020c Line Control Register 0x0000.0000 Reserved 0xFFF8.0210 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 144: Functional Descriptions

    LCR register is set 1. The driver should program, the correct value into the DLL/DLM registers according to the desired baud rate. Table 11-1 lists some general baud rate settings. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 145: Initializations

    TX, RX and RLS interrupts need to be enabled. Figure 11-1 shows the initialization flow of UART. Figure 11-1 UART initialization The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 146 THREIE : Transmit Holding Register Empty Interrupt Enable RADIE : Receive Data Available Interrupt Enable and Time-out Interrupt Enable. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 147: Polled I/O Functions

    Figure 11-2 Transmit data in polling mode Start Read LSR TE== 1 ? Write 16 data bytes to THR The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 148: Interrupted I/O Functions

    Tx FIFO when the transmitter FIFO empty interrupt occurs, or get the data bytes The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 149: Figure 11-4 Output Function In Interrupt Mode

    The Figure 11-4, Figure 11-5 and Figure 11-6 show the flow of output function, input function, and interrupt service routine. Figure 11-4 Output function in interrupt mode The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 150: Figure 11-5 Input Functions In Interrupt Mode

    Return the number of written data bytes Figure 11-5 Input functions in interrupt mode The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 151 Read the dresired numbers ? Return the number of read data bytes The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 152: Figure 11-6 Interrupt Service Routine

    Move data byte from Rx FIFO to driver buffer Disable THRE interrupt Read LSR The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 153: Irda Sir

    Move data byte Read LSR from Rx FIFO to driver buffer Disable THRE interrupt The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 154: Timers

    Normally, the program should implement a task to periodically reset the counter if the watchdog timer is enabled. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 155: Block Diagram

    Timer Initial Control Register 1 0x0000.0000 TICR1 0xFFF8.1010 R Timer Data Register 0 0x0000.0000 TDR0 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 156: Functional Descriptions

    • In one-shot mode, the interrupt signal is generated once and it’s not happen again unless the timer is re-enabled later. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 157 • In toggle mode, the interrupt signal is generated on each low-to-high or high-to-low transition with 50% duty cycle. Figure 12-2 shows the initialization sequence. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 158: Figure 12-2 Timer Initialization Sequence

    TICR Register Set Counter 23:0 Counter Set [CE] and [IE] of Enable Timer TCRx The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 159: Timer Interrupt Service Routine

    [1] TIF1: If TIF1 bit is 1, write TIF1 bit by 0 to clear Timer 1 interrupt The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 160: Watchdog Timer

    + 1024 clocks 4.47 sec 17 msec clocks + 1024 clocks 17.9 sec 70 msec The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 161: Figure 12-4 Enable Watchdog Timer

    WTIS : WatchDog Timer Interrupt Select WatchDog Timer WTRE : WatchDog Timer Reset Enable WTR : WatchDog Timer Reset The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 162: Figure 12-5 Watchdog Timer Isr

    // Reset WatchDog Timer by Setting Bit 0 2. WTCR = WTCR | 0x1; The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 163: Aic (Advanced Interrupt Controller)

    The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 164: Block Diagram

    ( A I C _ I E N C ) n F I Q The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 165: Registers

    0xFFF8.2068 Source Control Register 26 0x0000.0047 AIC_SCR26 0xFFF8.206C Source Control Register 27 0x0000.0047 AIC_SCR27 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 166 0xFFF8.2130 End of Service Command Register Undefined AIC_EOSCR 0xFFF8.2200 ICE/Debug mode Register Undefined AIC_TEST The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 167: Functional Descriptions

    Enable Command Register (AIC_MECR) is used to enable interrupt. Write 1 to a bit of MECR will The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 168: Interrupt Clearing And Setting

    When the interrupt is recognized by CPU core, the FIQ or IRQ exception handler is The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 169 Figure 13-3 demonstrates a sequential priority scheme where channel 1 has the highest priority and channel 17 18 has the lowest priority. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 170: Figure 13-3 Sequential Priority Scheme

    Interupt Service Mask != 0 ? Routine Mask <<= 1; Mask == 0x40000 ? The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 171: Hardware Priority Scheme

    AIC service the interrupt channel with lower priority. This hardware priority control is helpful to implement a nesting interrupt system. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 172: Figure 13-4 Interrupt Service Routine With Vector

    Int18_Interrupt Int19_Interrupt Int20_Interrupt Int21_Interrupt Int22_Interrupt Int23_Interrupt Int24_Interrupt Int25_Interrupt Int26_Interrupt Int27_Interrupt Int28_Interrupt Int29_Interrupt Int30_Interrupt Int31_Interrupt The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 173: Figure 13-5 Using Hardware Priority Scheme

    Service Routine W rite by Any Value to end this interrupt service W rite AIC_EOSCR The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 174: General-Purpose Input/Output (Gpio)

    AC97_nRESET (I2S_MCLK) nIRQ4 USBPWREN GPIO1 AC97_DATAI (I2S_DATAI) PWM0 DTR3 GPIO2 AC97_DATAO (I2S_DATAO) PWM1 DSR3 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 175 VD14 GPIO59 VD15 GPIO68 nWBE2/SDQM2 GPIO69 nWBE3/SDQM3 GPIO70 nWAIT nIRQ5 PORT5 Configuration Pin Functions The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 176: Register Map

    0xFFF8.302C GPIO port2 data input register 0x0000.0000 GPIO_CFG3 0xFFF8.3030 GPIO port3 configuration register 0x0000.5555 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 177: Functional Description

    GPIO_CFG=GPIO_CFG&0xFF3;// Clean PT0CFG1 GPIO_CFG=GPIO_CFG|(0x2<<2); // Set PT0CFG1 as PWM0 outpw(xFFF83000,GPIO_CFG);// Write value to GPIO_CFG0 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 178: Gpio Output Mode

    // set GPIO1 output 0 GPIO_CFG=inpw(0xFFF83008);// Get GPIO_DATAOUT0 value GPIO_CFG=GPIO_CFG&(0<<1);// GPIO1 output 0 outpw(xFFF83008,GPIO_CFG);// Write value to GPIO_DATAOUT0 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 179: Gpio Input Mode

    1.”); else printf(“GPIO pin1 input value is 0.”); The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 180 VERSION: PAGE: W90P710 Programming Guide The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 181: Real Time Clock (Rtc)

    Beside FCR, all clock and alarm data expressed in BCD code Support tick time interrupt The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 182: Block Diagram

    0x0000.0000 RTC_CLR 0xFFF8.4010 Calendar Loading Register 0x0005.0101 RTC_TSSR 0xFFF8.4014 Time Scale Selection Register 0x0000.0001 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 183: Functional Description

    User can utilize a frequency counter to measure RTC clock in one of GPIO pin during manufacture, and store the value in Flash memory for retrieval when the product is first power on. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 184: Application Note

    32764 0011 32771 1010 32763 0010 32770 1001 32762 0001 32769 1000 32761 0000 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 185: Programming Note

    Set hour, minute and second to register TLR Write 0x0 to AER means disable RTC access enable/disable password The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 186: Figure 15-2 Rtc Set Calendar And Time Flow Chart

    (TSSR) Set time, day and calendar (TLR, DWR, CLR) Disable RTC register R/W (AER) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 187: Set Calendar And Time Alarm

    Set the bit 0 of RIER for alarm interrupt enable Write 0x0 to AER means disable RTC access enable/disable password The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 188: Figure 15-3 Rtc Set Calendar And Time Alarm Flow Chart

    (TAR, CAR) Set alarm interrupt enable (RIER) Disable RTC register R/W (AER) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 189: Set Tick Interrupt

    Write 0x0 to AER means disable RTC access enable/disable password Figure 15-4 RTC Set tick interrupt flow chart The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 190 (bit 16 of AER be high?) Set interrupt tick number (TTR) Set tick interrupt enable (RIER) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 191: Smart Card Host Interface

    Reset Value Smartcard Host Interface 0 SCHI_RBR0 0xFFF8.5000 BDLAB =0 Receiver Buffer Register Undefined The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 192 SCHI_ECR1 0xFFF8.581C R/W Extended Control Register 0x0000.0052 SCHI_TMR1 0xFFF8.5820 R/W Test Mode Register 0x0000.0000 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 193: Functional Description

    5. Clear bit PWRDN of register SCHI_IER. 6. Set SC_REST of register SCHI_SCSR after 40000 clock cycles. 7. Process ATR. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 194: Timers Usage

    START bit. The timer is stopped by writing 3b’000 in register SCHI_TOC . The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 195 120 ETU (include first received character transmitting time: 12 ETU), the card can be considered as mute. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 196: Receiver Fifo Data Time-Out

    4 data characters in the receiver FIFO, an interrupt is activated to notify host to read data from FIFO. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 197: Parity Error Management

    2. If a correct character is received before the programmed error number is reached, the error counter will be reset The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 198 2. In reception the character with parity error enter into the receiver FIFO and the pin I/O is not NACK. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 199: C Synchronous Serial Interface Controller

    Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer Software programmable acknowledge bit The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 200 Supports 7 bit addressing mode Fully static synchronous design with one clock domain Software mode I The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 201: Block Diagram

    Control and Status Register 0x0000.0000 I2C_CSR1 I2C_DIVIDER1 0xFFF8.6104 Clock Prescale Register 0x0000.0000 0xFFF8.6108 Command Register 0x0000.0000 I2C_CMDR1 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 202: Functional Description

    TxR and set the WRITE bit in CMDR register. The core will then transfer the slave address on the bus. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 203: Data Transfer

    P = STO P c ondit ion The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 204 3. Write data and receive acknowledge from slave for n times 4. Generate stop command The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 205 Read a byte of data from an I2C memory device (Random read) Slave address = 0x4E (7'b1001110) Memory location to read from = 0x20 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 206 11. Set READ bit, set ACK to '1' (NACK), and set STOP bit of CMDR register. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 207 Commands: 1. Write a value into DIVIDER register to determine the frequency of serial clock. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 208 19. Read out received final data from RxR register, it will put on RxR[7:0]. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 209: Universal Serial Interface

    Rx and Tx on both rising or falling edge of serial clock independently 2 slave/device select lines Fully static synchronous design with one clock domain The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 210: Block Diagram

    R : read only, W : write only, R/W : both read and write, C : Only value 0 can be written Register Address Description Reset Value The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 211: Functional Description

    To initial the Universal Serial Interface, please follow the steps below: 1. Set USI_DIVIDER register to generate the serial clock on output clock The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 212: Universal Serial Interface Transmit/Receive

    2. Activate the Universal Serial Interface 3. Receive the data from USI_Rx0 ~ USI_Rx3 registers The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 213: Pulse Width Modulation (Pwm) Timer

    The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
  • Page 214 Two 8-bit prescalers and two clock dividers Four clock selectors Four 16-bit counters and four 16-bit comparators Two Dead-Zone generator The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 215: Block Diagram

    CNR1 0xFFF8.7018 PWM Counter Register 1 0000.0000 CMR1 0xFFF8.701C PWM Comparator Register 1 0000.0000 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 216: Functional Description

    Maximum period: PPR=255(since the length of PPR is 8bit) and CSR=16 period ÷ ÷ Minimum period: PCLK=80 MHz, PPR=1 and CSR=1 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 217: Basic Pwm Timer Operation And Double Buffering Reload Automatically

    If CNR0~3 are set as zero, counter will be halt when counter count to zero. If auto-reload bit is set as zero, counter will be stopped immediately. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 218: Pwm Timer Start Procedure

    11. Enable pwm timer ( PCR ) A flowchart of this procedure is given in the following figure. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 219: Figure 19-3 Pwm Timer Start Procedure

    Setup inverter on/off toggle mode/one-shot mode Setup CNR, CMR Setup PIER Start PWM timer The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 220: Pwm Timer Stop Procedure

    (PWM_CNRx) Wait for count down data be zero (PWM_PDRx) Disable PWM timer (PWM_PCR) stop The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 221: Figure 19-5 Pwm Timer Stop Flow Chart (Method 2)

    (PWM_CNRx) Wait for interrupt happen (PWM_PIIR) Disable PWM timer (PWM_PCR) stop The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 222: Keypad Interface

    8x8 or 4x8 key array. If the 4x8 array is selected then external decoder is not necessary because the scan signals are derived by W90P710 itself. Any 1 or 2 keys in the array that pressed are debounced and encoded. If more than 2 keys are pressed, only the keys or apparent keys in the array with the lowest address will be decoded.

  • Page 223: Block Diagram

    Keypad controller low power configuration 0x0000.0000 register KPISTATUS 0xFFF8.800C Keypad controller status register 0x0000.0000 20.4 Functional Description The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 224: Kpi Interface Programming Flow

    Wait for keypad flag set by KPI ISR Get KPI row and column value in register KPISTATUS , then go back to step 5 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 225: Kpi Low Power Mode Configuration

    Programming need to set WAKE bit and configure LPWCEN[15:8] and LPWR[3:0] register KPILPCONF for enable wake up function. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 226: Figure 20-3 Kpi Set Wake-Up In System Low Power Mode Flowchart

    4’b1000.., and Specify columns for low power wakeup ( LPWCEN[15:8] ). For example, if user wants to use kyes in row N and column 0, 2, 5 to wake up W90P710, then the LPWCEN should be fill 8’b00100101. Figure 20-3 shows the flowchart.

  • Page 227: Ps/2 Host Interface Controller

    The following figures show the key map of scan code set two. All the scan codes are shown in Hex. Figure 21-1 Key map of PS/2 keyboard The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 228: Figure 21-2 Key Map Of Extended Keyboard & Numeric Keypad

    E0h. In addition to every key having its own unique make code, they all have their own unique break code. And certain relationships exist between make codes and break codes. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 229: Register Map

    PS/2 interface. After that, the software driver can send a reset command to reset a PS/2 device. 1. Configure GPIO_CFG5 (0xFFF83050) : set bits 11 ~ 8 to 0xF The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 230: Send Commands

    Resend - Upon receipt of the resend command the keyboard will re- transmit the last byte sent. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 231: Read Scan Code And Ascii Code

    The host controller will put the received scan code into field RX_SCAN_CODE . But note that the host controller will not report “Extend” (0xE0) or “Break” (0xF0) scan code in this The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 232: Interrupt Service Routine

    PS2STS. The status shows a scan code arrived or a command has been sent. Table 21-5 Register PS2ST RESERVED RESERVED The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

  • Page 233: Figure 21-4 Example Isr

    TRAP_SHIFT bit of PS2_CMD register. The following figure illustrates an example interrupt service routine. Figure 21-4 Example ISR The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...
  • Page 234 2. Read interrupt status from register PS2STS 3. If RX_IRQ is set go to step 3, otherwise go to step 4 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.

  • Page 235: Example

    Table 21-6 LED Status byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Caps Scroll Lock Lock Lock The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Table No.: 2005-W90P710-11-A...

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