Winbond W90P710 Manuals

Manuals and User Guides for Winbond W90P710. We have 1 Winbond W90P710 manual available for free PDF download: Programming Manual

Winbond W90P710 Programming Manual

Winbond W90P710 Programming Manual (235 pages)

Brand: Winbond | Category: Microcontrollers | Size: 2 MB

Table of Contents

Table of Contents
3
1 Overview

15
- Figure 1-1 W90P710 Functional Block Diagram
  16
  - Features
    18
    
    Architecture
    18
    
    External Bus Interface
    18
    
    Instruction and Data Cache
    18
    
    Ethernet MAC Controller
    18
    
    DMA Controller
    19
    
    USB Host Controller
    19
    
    USB Device Controller
    19
    
    SDIO Host Controller
    19
    
    LCD Controller
    20
    
    Channel AC97/I2S Audio Codec Host Interface
    21
    
    Uart
    21
    
    Timers
    21
    
    Advanced Interrupt Controller
    21
    
    Gpio
    22
    
    Real Time Clock
    22
    
    Smart Card Host Interface
    22
    
    I2C Master
    23
    
    Universal Serial Interface (USI)
    23
    
    4-Channel PWM
    23
    
    Keypad Interface
    24
    
    PS2 Host Interface Controller
    24
    
    Power Management
    24
2 EBI (External Bus Interface)

25
- Overview
  25
- Block Diagram
  26
  - SDRAM Interface
    26
  - Figure 2-1 SDRAM Interface
    26
- Registers
  27
- Functional Descriptions
  27
3 Cache Controller

35
- Overview
  35
- Block Diagram
  36
- Figure 3-1 Instruction Cache Organization Block Diagram
  36
- Figure 3-2 Data Cache Organization Block Diagram
  37
- Registers
  38
- Functional Descriptions
  38
  - On-Chip RAM
    38
  - Table 3-1 the Size and Start Address of On-Chip RAM
    38
  - Non-Cacheable Area
    39
  - Cache Flushing
    39
  - Cache Enable and Disable
    39
  - Cache Load and Lock
    40
  - Figure 3-3 Cache Load and Lock
    40
  - Cache Unlock
    41
4 EMC (Ethernet MAC Controller)

42
- Overview
  42
- Block Diagram
  43
- Figure 4-1 EMC Block Diagram
  43
- Registers
  44
  - EMC Control Registers
    44
  - EMC Status Registers
    45
- Functional Descriptions
  45
5 Gdma

58
- Overview
  58
- Block Diagram
  59
- Figure 5-1 GDMA Block Diagram
  59
- Registers
  60
- Functional Descriptions
  60
  - GDMA Configuration
    60
  - Figure 5-2 the Bit-Fields of the GDMA Control Register
    61
  - Transfer Count
    62
  - Figure 5-3 GDMA Operations
    62
  - Transfer Termination
    63
  - GDMA Operation Started by Software
    63
  - Figure 5-4 Software GDMA Transfer
    64
  - GDMA Operation Started by Nxdreq
    65
  - Fixed Address
    66
  - Block Mode Transfer
    66
  - Single Mode Transfer
    66
  - Demand Mode Transfer
    66
6 USB Host Controller

68
- Overview
  68
- Registers Map
  69
- Block Diagram
  70
- Data Structures
  71
- Programming Note
  76
  - Initialization
    76
  - USB States
    77
  - Add/Remove Endpoint Descriptors
    78
  - Figure 6-4 Remove an Endpoint Descriptor
    79
  - Add/Remove Transfer Descriptors
    80
  - Figure 6-5 ED List and TD Queue
    80
  - IRP Processing
    82
  - Interrupt Processing
    84
  - Done Queue Processing
    88
  - Root Hub
    90
7 USB Device Controller

94
- Overview
  94
- Block Diagram
  95
- Register Map
  95
- Figure 7-1 USBD Controller Block Diagram
  95
- Functional Descriptions
  97
  - Initialization
    97
  - Endpoint Configuration
    98
  - Interrupt Service Routine
    98
  - Endpoint 0 Operation
    99
  - Figure 10-2 USBD Controller Block Diagram
    99
  - Get Descriptor
    100
  - Endpoint a ~ C Operation
    101
  - Example
    102
8 SDIO Host Controller

103
- Overview
  103
- Block Diagram
  103
- Figure 8-1 SDIO Host Block Diagram
  103
- Registers
  104
- SDIO Host Controller
  105
- SD Host Interface
  106
  - Send Command to SD/MMC Card
    106
  - Get Response from SD/MMC Card
    107
  - SD/MMC to Buffer Access
    107
  - Buffer to SD/MMC Access
    107
9 LCD Controller

108
10 Audio Controller

128
- Overview
  128
- Block Diagram
  129
- Figure 10-1 Block Diagram of Audio Controlle
  129
- Registers
  130
- AC97 Interface
  130
  - Table 10-1 AC97 Output Frame
    131
  - Table 10-2 AC97 Output Frame Data Format
    131
  - Table 10-3 AC97 Input Frame
    131
  - Cold Reset External AC97 Codec
    132
  - Read AC97 Registers
    132
  - Table 10-4 AC97 Input Frame Data Format
    132
  - Write AC97 Registers
    134
  - AC97 Playback
    135
  - Figure 10-2 AC97 Playback Data in DMA Buffer
    135
  - AC97 Record
    137
  - Figure 10-3 AC97 Data in Record DMA Buffer
    137
- I2S Interface
  138
  - I2S Play
    138
  - Figure 10-4 I2S Play Data in DMA Buffer
    139
  - I2S Record
    140
  - Figure 10-5 I2S Record Data in DMA Buffer
    140
11 Uart

142
- Overview
  142
- Registers
  142
- Functional Descriptions
  144
  - Baud Rate
    144
  - Initializations
    145
  - Figure 11-1 UART Initialization
    145
  - Table 11-1 General Baud Rate Settings
    145
  - Polled I/O Functions
    147
  - Figure 11-2 Transmit Data in Polling Mode
    147
  - Interrupted I/O Functions
    148
  - Figure 11-3 Receive Data in Polling Mode
    148
  - Figure 11-4 Output Function in Interrupt Mode
    149
  - Figure 11-5 Input Functions in Interrupt Mode
    150
  - Figure 11-6 Interrupt Service Routine
    152
  - Irda SIR
    153
  - Figure 11-7 Irda Tx/Rx
    153
12 Timers

154
- Overview
  154
- Block Diagram
  155
- Registers
  155
- Figure 12-1 Timer Block Diagram
  155
- Functional Descriptions
  156
  - Interrupt Frequency
    156
  - Initialization
    156
  - Table 12-1 Timer Reference Setting Values
    156
  - Figure 12-2 Timer Initialization Sequence
    158
  - Timer Interrupt Service Routine
    159
  - Figure 12-3 Timer Interrupt Service Routine
    159
  - Watchdog Timer
    160
  - Figure 12-4 Enable Watchdog Timer
    161
  - Figure 12-5 Watchdog Timer ISR
    162
13 AIC (Advanced Interrupt Controller)

163
- Overview
  163
- Block Diagram
  164
- Figure 13-1 AIC Block Diagram
  164
- Registers
  165
- Table 13-1 AIC Register Definition
  165
- Functional Descriptions
  167
  - Interrupt Channel Configuration
    167
  - Interrupt Masking
    167
  - Figure 13-2 Source Control Register
    167
  - Interrupt Clearing and Setting
    168
  - Software Priority Scheme
    168
  - Figure 13-3 Sequential Priority Scheme
    170
  - Hardware Priority Scheme
    171
  - Figure 13-4 Interrupt Service Routine with Vector
    172
  - Figure 13-5 Using Hardware Priority Scheme
    173
14 General-Purpose Input/Output (GPIO)

174
- Overview
  174
- Table 14-1 GPIO Multiplexed Functions Table
  174
- Register Map
  176
- Functional Description
  177
  - Multiple Functin Setting
    177
  - GPIO Output Mode
    178
  - GPIO Input Mode
    179
15 Real Time Clock (RTC)

181
- Overview
  181
- Block Diagram
  182
- Register Map
  182
- Figure 15-1 RTC Block Diagram
  182
- Functional Description
  183
  - Initialization
    183
  - RTC Read/Write Enable
    183
  - Frequency Compensation
    183
  - Application Note
    184
- Programming Note
  185
16 Smart Card Host Interface

191
- Overview
  191
- Registers
  191
- Functional Description
  193
  - Initialization Sequence
    193
  - Timers Usage
    194
  - Receiver FIFO Data Time-Out
    196
  - Parity Error Management
    197
17 I C Synchronous Serial Interface Controller

199
- C Synchronous Serial Interface Controller
  199
  - Overview
    199
  - Block Diagram
    201
  - Register Map
    201
  - Figure 17-1 I C Block Diagram
    201
  - Functional Description
    202
    
    Prescale Frequency
    202
    
    Start and Stop Signal
    202
    
    Slave Address Transfer
    202
    
    Data Transfer
    203
    
    Below List some Examples of I2C Data Transaction
    203
18 Universal Serial Interface

209
- Overview
  209
- Block Diagram
  210
- Register Map
  210
- Figure 18-1 Universal Serial Interfacei Block Diagra
  210
- Functional Description
  211
19 Pulse Width Modulation (PWM) Timer

213
- Overview
  213
- Block Diagram
  215
- Register Map
  215
- Figure 19-1 PWM Block Diagram
  215
- Functional Description
  216
20 Keypad Interface

222
- Overview
  222
- Block Diagram
  223
- Register Map
  223
- Functional Description
  223
21 PS/2 Host Interface Controller

227
- Overview
  227
- Scan Code Set
  227
- Figure 21-1 Key Map of PS/2 Keyboard
  227
- Figure 21-2 Key Map of Extended Keyboard & Numeric Keypad
  228
- Register Map
  229
- Functional Description
  229
  - Initialization
    229
  - Figure 21-3 Make Code and Break Code
    229
  - Send Commands
    230
  - Table 21-1 Command Register PS2CMD
    230
  - Table 21-2 Command Table
    230
  - Read Scan Code and ASCII Code
    231
  - Table 21-3 Register PS2SCANCODE
    231
  - Interrupt Service Routine
    232
  - Table 21-4 Register PS2ASCII
    232
  - Table 21-5 Register PS2ST
    232
  - Figure 21-4 Example ISR
    233
  - Example
    235
  - Table 21-6 LED Status Byte
    235

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