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GENERAL DESCRIPTION
The W928C73 is a high performance 8 bits microcontroller with build-in POCSAG decoder and LCD
driver. It is possible to switch the normal mode, idle mode and power down mode for power saving
purpose. The W928C73 is an extended µC from standard 8031 (excluding UART) that it can be easily
applied to pager system or other telecommunication system.
FEATURES
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512, 1200 and 2400 bps POCSAG decoder
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6 independent user addresses
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Instruction set compatible with MCS51
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System clock
− OSC2: 76.8 KHz
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128 bytes on-chip fast RAM
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384 bytes on-chip MOVX RAM
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16K bytes on-chip program ROM
32 × 32 bits on-chip flash RAM
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Timer
− Two 16-bit timer/counters
− One RTC timer
− One Watch-dog timer
− One Buzzer timer
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Four 8-bit bit-addressable I/O ports
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Three external interrupt source, INT0, INT1 (BAT_DET_INT), INT3 (KEY_INT)
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Battery low detector
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Battery detector
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Power fail detector
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Power down wake-up via external interrupts
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Two 16-bit Data Pointers (Selected by DPS.0)
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10 source, 10 vector interrupts structure with two priority-level interrupts
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Built-in programmable power-saving modes - Idle mode & Power-down mode
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Operating voltage range: 2.4V to 3.3V
32 segment × 4 common, 1/3 bias, 1/4 duty LCD driver output
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Packaged in 64-pin LQFP
Preliminary W928C73
POCSAG MICROCONTROLLER
- 1 -
Publication Release Date: June 2000
Revision A1
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Table of Contents
Related Manuals for Winbond W928C73
Summary of Contents for Winbond W928C73
- Page 1 It is possible to switch the normal mode, idle mode and power down mode for power saving purpose. The W928C73 is an extended µC from standard 8031 (excluding UART) that it can be easily applied to pager system or other telecommunication system.
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Page 2: Pin Configuration
Preliminary W928C73 PIN CONFIGURATION SEG29 SEG28 RESET SEG27 P1.5/MOTOR SEG26 P1.6/BUZZER SEG25 P1.7/LED SEG24 BL_RF SEG23 W928C73 SEG22 64 LQFP SEG21 SEG20 SEG19 SEG18 TEST1 SEG17 TEST2 SEG16 PSEN SEG15 P3.0 SEG14 P3.1 - 2 -... -
Page 3: Pin Descriptions
Preliminary W928C73 PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTIONS GROUND: ground potential RESET: A low on this pin for two machine cycles while the oscillator is running resets the device. P1.5 Motor output, hi-drive P1.6 Buzzer clock output, hi-drive P1.7 LED output, hi-drive... - Page 4 Preliminary W928C73 Pin Descriptions, continued SYMBOL TYPE DESCRIPTIONS SEG14 LCD segment signal out SEG15 LCD segment signal out SEG16 LCD segment signal out SEG17 LCD segment signal out SEG18 LCD segment signal out SEG19 LCD segment signal out SEG20 LCD segment signal out...
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Page 5: Block Diagram
Preliminary W928C73 BLOCK DIAGRAM Port Port P0.3 P2.5 P2.7 P0.7 P4.0~4.7 T1 register T2 register P1.0 P5.0~5.7 Port P1.2 Port P6.0~6.7 Stack P1.5 P7.0~7.7 Pointer P8.0~8.3 P1.7 P3.0 Port LCD_OFF P3.3 DPTR 128B MOV RAM DPTR 1 LCD_ON 384B MOVX RAM... -
Page 6: Functional Description
POCSAG decoder. The uC is 8031 instruction set compatible with one addition: DEC DPTR (op-code A5H, the DPTR is decreased by 1). The W928C73 has all the standard features of the 8031 except the UART, and has a few extra peripherals and features like watchdog, RTC, buzzer timers, LCD driver, and build-in POCSAG decoder. - Page 7 Preliminary W928C73 LCD Data Area When LCD ON, the indirect RAM area EEH−FFH work as the LCD data RAM (LCD00−LCD35). Instruction such as "MOV @R0, #I" (Where R0 = EEH−FFH) are used to control the LCD data RAM. The data in the LCD data RAM (bit7−bit0) are transferred to the segment output pins automatically without program control.
- Page 8 Preliminary W928C73 Descriptions Of Special Function Registers(SFRS) ADDRESS BIT NAME INITIAL FUNCTION /NAME 80H/P0 No use Key_2 Key_2 input. A corresponding key_INT(INT3_3) can be enabled. Key_1 Key_1 input. A corresponding key_INT(INT3_3) can be enabled. Key_0 Key_0 input. A corresponding key_INT(INT3_3) can be enabled.
- Page 9 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS BIT NAME INITIAL FUNCTION /NAME High level Low level Interrupt 1 level selection. Set by software to specify high (>0.8V) / low (<0.8V) level external INT 1 triggered. No INT Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0.
- Page 10 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS BIT NAME INITIAL FUNCTION /NAME Set B3 and B2 to 1 after power on reset. Enable Disable ELC: enable L_clock. Keep this bit high for whole operation. Clear to “0” after reset.
- Page 11 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS BIT NAME INITIAL FUNCTION /NAME P2.0 High No use if SEG35~32 work as LCD segment. I/O P2.0 value if SEG35~32 work as P2.3~P2.0 function (P2M (A1.1H) = 0) A1H/LCDR LCDWAVE...
- Page 12 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS BIT NAME INITIAL FUNCTION /NAME B0H/P3 DEC_BL Battery Battery Battery condition. If battery voltage is lower than 1 volt, this bit will change to 1, otherwise this bit will be 0.
- Page 13 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS BIT NAME INITIAL FUNCTION /NAME C4H/SB3 B7~0 00000000 POCSAG receiving buffer 3 C9H/T2MOD DME0 On-chip External MOVX RAM selection (384 bytes), set to 1 after reset Clear this bit to "0" after reset Clear this bit to "0"...
- Page 14 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS BIT NAME INITIAL FUNCTION /NAME D8H/WDCON WDIF Watchdog Timer Interrupt Flag: If the watchdog interrupt is enabled, hardware will set this bit to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit indicates that the time-out period has elapsed.
- Page 15 Preliminary W928C73 Descriptions Of Special Function Registers (SFRS), continued ADDRESS BIT NAME INITIAL FUNCTION /NAME DAH/P1IO B7~0 P1IO 00000000 Bit addressable R/W control for P1: 1: input mode without pull high R 0: output mode or input with pull high R Set DA to “00000000 “...
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Page 16: System Clock
Preliminary W928C73 Data Pointers The original 8031 had only one 16-bit Data Pointer (DPL, DPH). In the W928C73, there is an additional 16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations which were unused in the original 8031. In addition there is an additional instruction, DEC DPTR (op-code A5H), which helps in improving programming flexibility for the user. -
Page 17: Operation Mode
Preliminary W928C73 Power Management Operation Mode (Normal Mode) After the power on reset, the W928C73 will enter the normal operation mode. In this mode, all the system is operable with the main clock. Idle Mode While setting the PCON.0 to 1, the system will go to idle mode. In idle mode, the CPU is stopped but rest of the system and the oscillator is still running as previous state The idle mode can be waked up by all the interrupt sources. - Page 18 Timer 0 & 1 The W928C73 has two 16-bit Timer. Each of these Timer has two 8 bit registers which form the 16 bit counting register. For Timer 0 they are TH0, the upper 8 bits register, and TL0, the lower 8 bit register.
- Page 19 Preliminary W928C73 Mode 1 Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13 bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer moves from a count of FFFFh to 0000h.
- Page 20 RWT:D8.0H Buzzer Timer The W928C73 provides a buzzer timer. The buzzer timer can output a single tone signal to the BUZ pin that frequency range from 150Hz to 38400 Hz. The operation of buzzer timer is as following. First set the proper value of tone0 then set the ENBUZ to 1, the uC will output the corresponding frequency (50% duty cycle) to P1.6/BUZ output pin.
- Page 21 LCD Controller/Driver The W928C73 can directly drive a LCD with 32 segment output pins and 4 common output pins for a total of 36 × 4 dots. LCDR is used for the LCD driver control. The alternating frequency of the LCD can be set as 64 Hz, 128 Hz, 256 Hz, or 512 Hz.
- Page 22 When clear to 0 will set the I/O port as input mode with pull high resister or output mode. Port 0 − port 3 are bit addressable. The initial state of W928C73 is input mode with pull high resister.
- Page 23 Preliminary W928C73 Initial Option Bit Setup The decoder should be initialized through SFR DEC_TXCLK (P1.0), DEC_TXDATA (P1.1), and DEC_RST (P1.3) as Fig 12. Clearing the SFR DEC_ON (P1.2) from high to low after the 192 option bits setting will enable the decoder. The BS1, BS2 and BS3 pins will then control the RF to receive POCSAG signal.
- Page 24 Preliminary W928C73 POCDSG Decoder Setup Option CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA D128 D160 TEST0 D129 D161 TEST1 D130 D162 ADA17 ADB17 ADC17 ADD17 D131 ADE17 D163 ADF17 ADA16 ADB16 ADC16 D100 ADD16 D132...
- Page 25 Preliminary W928C73 FUNCTION OPTION Address A, B, C, D, E, F EnA, EnB, EnC, EnD, EnE, EnF Disable Enable FUNCTION OPTION Message reception error termination condition Over1 Over0 Reception termination on first uncorrectable codeword Reception termination on two consecutive uncorrectable codeword...
- Page 26 Preliminary W928C73 32 bits FUNCTION OPTION 512 bps 1200/2400 bps 3.90 mS 1.67 mS 11.71 mS 5.00 mS 19.53 mS 8.33 mS 27.34 mS 11.67 mS FUNCTION OPTION 512 bps 1200/2400 bps 0.00 mS 0.00 mS 31.25 mS 13.33 mS 62.50 mS...
- Page 27 Preliminary W928C73 FUNCTION OPTION NRZ signal Non-inversion Inversion The option bit TEST0, TEST1 and FIL are only used for IC testing. For normal operation, insert “0” for all those three option bits. POCSAG data output format While receiving an address matched message the SCON1 will generate interrupt and the data will present in SBUF1−3.
- Page 28 Preliminary W928C73 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADR2 ADR1 ADR0 CM (0) Note: CM = 0: Address word, CM = 1: Message word, Termination word Func21, 20: function bit of POCSAG ADR2~0: define the received address number ADR2−0...
- Page 29 Battery low detector (1V) 32 x 32 bits Flash ROM Operation The W928C73 provides 32 frame × 32 bit flash ROM cell typically used to store the POCSAG addresses and parameters. The single voltage supply eliminates the need for an extra pump circuit during programming and erasing.
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Page 30: Timing Waveforms
Preliminary W928C73 Read mode This mode will read out the data from the flash ROM. The first 24 bits of DATA are the starting frame address of reading-out. If DATA is low for these 24 bits, then the output data will start from address "0". - Page 31 Preliminary W928C73 Flash Programming SFR Configuration SFR NAME NAME DESCRIPTION P0.0 DATA Bi-direction data line P0.2 ADDR Output clock for start address shift-out P3.4 CTRL Enable signal for program and erase operations when MODE = 0 (P3.6) Input clock for mode counter when MODE = 1 (P3.6) P3.5...
- Page 32 Preliminary W928C73 FLASH ROM AC CHARACTERISTICS = 3V, V = 0V, T = 25° C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT µS MODE Pulse Width µS CTRL Pulse Width Page coding mode Clock Frequency of ADDR ADDR Clock Frequency of CLK...
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Page 33: Application Circuit
Preliminary W928C73 APPLICATION CIRCUIT Key2 Key1 76.8K Key0 10 PF SEG29 RESET SEG28 Motor P1.5 SEG27 Buzzer SEG26 P1.6 SEG25 P1.7 From RF bat_det SEG24 BL_RF Signal_in SEG23 W928C73 RFEN SEG22 SEG21 64 LQFP PLEN SEG20 SEG19 TEST1 (NC) SEG18... - Page 34 Preliminary W928C73 Headquarters Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Memory Lab. Unit 9-15, 22F, Millennium City, Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No.
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