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Winbond W77E516 Manual

8-bit microcontroller
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Table of Contents-

1. GENERAL DESCRIPTION...........................................................................................................................3
2. FEATURES ..................................................................................................................................................3
3. PIN CONFIGURATIONS..............................................................................................................................4
4. PIN DESCRIPTION......................................................................................................................................5
5. BLOCK DIAGRAM .......................................................................................................................................6
6. FUNCTIONAL DESCRIPTION.....................................................................................................................7
I/O Ports.....................................................................................................................................................7
Serial I/O....................................................................................................................................................7
Timers........................................................................................................................................................8
Interrupts....................................................................................................................................................8
Data Pointers .............................................................................................................................................8
Power Management...................................................................................................................................8
On-chip Data SRAM ..................................................................................................................................8
7. MEMORY ORGANIZATION .........................................................................................................................8
Program Memory .......................................................................................................................................8
Data Memory .............................................................................................................................................9
Special Function Registers ......................................................................................................................10
Special Function Registers ......................................................................................................................11
Instruction ................................................................................................................................................34
Instruction Timing ....................................................................................................................................41
Power Management.................................................................................................................................49
Reset Conditions .....................................................................................................................................51
Reset State ..............................................................................................................................................52
Interrupts..................................................................................................................................................53
8. PROGRAMMABLE TIMERS/COUNTERS .................................................................................................56
Timer/Counters 0 & 1...............................................................................................................................56
Time-base Selection ................................................................................................................................57
Timer/Counter 2 .......................................................................................................................................59
Watchdog Timer ......................................................................................................................................62
Serial Port ................................................................................................................................................64
Framing Error Detection ..........................................................................................................................70
Multiprocessor Communications..............................................................................................................70
Preliminary W77E516
8-BIT MICROCONTROLLER
Publication Release Date: August 16, 2002
- 1 -
Revision A1

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  • Page 1: Table Of Contents

    Preliminary W77E516 8-BIT MICROCONTROLLER Table of Contents- 1. GENERAL DESCRIPTION...........................3 2. FEATURES ..............................3 3. PIN CONFIGURATIONS..........................4 4. PIN DESCRIPTION............................5 5. BLOCK DIAGRAM ............................6 6. FUNCTIONAL DESCRIPTION........................7 I/O Ports..............................7 Serial I/O..............................7 Timers................................8 Interrupts..............................8 Data Pointers .............................8 Power Management...........................8 On-chip Data SRAM ..........................8 7.
  • Page 2 Preliminary W77E516 9. TIMED ACCESS PROTECTION........................71 10. ABSOLUTE MAXIMUM RATINGS......................72 11. AC CHARACTERISTICS .........................74 External Clock Characteristics.........................74 AC Specification ............................74 MOVX Characteristics Using Strech Memory Cycles ................75 12. TIMING WAVEFORMS ..........................76 Program Memory Read Cycle........................76 Data Memory Read Cycle........................77 Data Memory Write Cycle........................77 13.

  • Page 3: General Description

    Consequently, the W77E516 is a fully static CMOS design; it can also be operated at a lower crystal clock. The W77E516 contains In-System Programmable (ISP) 64 KB Flash EPROM; 4KB auxiliary Flash EPROM for loader program;...

  • Page 4: Pin Configurations

    Preliminary W77E516 3. PIN CONFIGURATIONS 40-Pin DIP (W77E516) T2, P1.0 T2EX, P1.1 P0.0, AD0 RXD1, P1.2 P0.1, AD1 TXD1, P1.3 P0.2, AD2 INT2, P1.4 P0.3, AD3 P0.4, AD4 INT3, P1.5 P0.5, AD5 INT4, P1.6 INT5, P1.7 P0.6, AD6 P0.7, AD7 RXD, P3.0...

  • Page 5: Pin Description

    Preliminary W77E516 4. PIN DESCRIPTION SYMBOL TYPE DESCRIPTIONS EXTERNAL ACCESS ENABLE: It should be kept high for internal program access.. PROGRAM STORE ENABLE: PSEN enables the external ROM data onto PSEN the Port 0 address/data bus during fetch and MOVC operations.

  • Page 6: Block Diagram

    Preliminary W77E516 5. BLOCK DIAGRAM P1.0 Port Port 1 Port 0 P0.0 ∫ Latch Port Latch P1.7 ∫ T1 Register T2 Register Interrupt DPTR Stack DPTR 1 Pointer Timer Temp Reg. Address Timer Incrementor SFR RAM Address Timer Addr. Reg.

  • Page 7: Functional Description

    Consequently, the W77E516 can run at a higher speed as compared to the original 8052, even if the same crystal is used. Since the W77E516 is a fully static CMOS design, it can also be operated at a lower crystal clock, giving the same throughput in terms of instruction execution, yet reducing the power consumption.

  • Page 8: Timers

    8052. The W77E516 has an additional feature, the watchdog timer. This timer is used as a System Monitor or as a very long time period timer.

  • Page 9: Data Memory

    Any MOVX directed to the space between 0000H and FFFFH goes to the expanded bus on Port 0 and 2. This is the default condition. In addition, the W77E516 has the standard 256 bytes of on-chip Scratchpad RAM. This can be accessed either by direct addressing or by indirect addressing.
  • Page 10 Preliminary W77E516 Indirect RAM Direct RAM Bit Addressable 20H − 2FH Bank 3 Bank 2 Bank 1 Bank 0 Figure 2. Scratchpad RAM / Register Addressing - 10 -...

  • Page 11: Special Function Registers

    The SFRs that are bit addressable are those whose addresses end in 0 or 8. The W77E516 contains all the SFRs present in the standard 8052. However, some additional SFRs have been added. In some cases unused bits in the original 8052 have been given new functions. The list of SFRs is as follows.
  • Page 12 Mnemonic: DPL1 Address: 84h This is the low byte of the new additional 16-bit data pointer that has been added to the W77E516. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH.
  • Page 13 IDL: Setting this bit causes the W77E516 to go into the IDLE mode. In this mode the clocks to the CPU are stopped, so program execution is frozen. But the clock to the serial, timer and interrupt blocks is not stopped, and these blocks continue operating.
  • Page 14 Preliminary W77E516 TF1: Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear this bit. TR1: Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
  • Page 15 Preliminary W77E516 M1, M0: Mode Select bits: Mode Mode 0: 8-bits with 5-bit prescale. Mode 1: 18-bits, no prescale. Mode 2: 8-bits with auto-reload from THx Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
  • Page 16 Preliminary W77E516 Clock Control Bit: Mnemonic: CKCON Address: 8Eh WD1 − 0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt time-out period.
  • Page 17 Preliminary W77E516 Port 1 Bit: P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Mnemonic: P1 Address: 90h P1.7 − 0: General purpose I/O port. Most instructions will read the port pins in case of a port read access, however in case of read-modify-write instructions, the port latch is read. Some pins also have alternate input or output functions.
  • Page 18 Preliminary W77E516 BIT NAME FUNCTION P4xM1, P4xM0 Port 4 alternate modes. = 00: Mode 0. P4.x is a general purpose I/O port which is the same as Port 1. = 01: Mode 1. P4.x is a Read Strobe signal for chip select purpose. The address range depends on the SFR P4xAH, P4xAL and bits P4xC1, P4xC0.
  • Page 19 Preliminary W77E516 P4.1 Base Address High Byte Register Bit: Mnemonic: P41AH Address: 97h Serial Port Control Bit: SM0/FE Mnemonic: SCON Address: 98h SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE.
  • Page 20 Preliminary W77E516 Serial Data Buffer Bit: SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Mnemonic: SBUF Address: 99h SBUF.7 − 0: Serial data on the serial port 0 is read from or written to this location. It actually consists of two separate internal 8-bit registers. One is the receive resister, and the other is the transmit buffer.
  • Page 21 Preliminary W77E516 LDAP: This bit is Read Only. High: device is executing the program in LDROM. Low: device is executing the program in APROM. LDSEL: Loader program residence selection. Set to high to route the device fetching code from LDROM.
  • Page 22 Preliminary W77E516 EA: Global enable. Enable/disable all interrupts except for PFI. ES1: Enable Serial Port 1 interrupt. ET2: Enable Timer 2 interrupt. ES: Enable Serial Port 0 interrupt. ET1: Enable Timer 1 interrupt EX1: Enable external interrupt 1 ET0: Enable Timer 0 interrupt...
  • Page 23 Preliminary W77E516 ISP Data Buffer Bit: Mnemonic: SFRFD Address: AEh In ISP mode, read/write a specific byte ROM content must go through SFRFD register. ISP Operation Modes Bit: WFWIN CTRL3 CTRL2 CTRL1 CTRL0 Mnemonic: SFRCN Address: AFh WFWIN: Destination ROM bank for programming, erasure and read. 0 = APROM, 1 = LDROM.
  • Page 24 Preliminary W77E516 Interrupt Priority Bit: Mnemonic: IP Address: B8h IP.7: This bit is un-implemented and will read high. PS1: This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level. PT2: This bit defines the Timer 2 interrupt priority.
  • Page 25 Preliminary W77E516 SM0_1/FE_1: Serial port 1, Mode 0 bit or Framing Error Flag 1: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0_1 or as FE_1, the operation of SM0_1 is described below. When used as FE_1, this bit will be set to indicate an invalid stop bit.
  • Page 26 Preliminary W77E516 WS: Wait State Signal Enable. Setting this bit enables the WAIT signal on P4.0. The device will sample the wait state control signal WAIT via P4.0 during MOVX instruction. This bit is time access protected. WSCON CKCON TA, #AAH TA, #55H WSCON, #10000000B;...
  • Page 27 Preliminary W77E516 Status Register Bit: XTUP SPTA1 SPRA1 SPTA0 SPRA0 Mnemonic: STATUS Address: C5h HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction.
  • Page 28 Preliminary W77E516 Timed Access Bit: TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TfA.0 Mnemonic: TA Address: C7h TA: The Timed Access register controls the access to protected bits. To access protected bits, the user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.
  • Page 29 Preliminary W77E516 CP RL 2 : Capture/Reload Select. This bit determines whether the capture or reload function will be used for timer 2. If either RCLK or TCLK is set, this bit will be ignored and the timer will function in an auto-reload mode following each overflow. If the bit is 0 then auto-reload will occur when timer 2 overflows or a falling edge is detected on T2EX pin if EXEN2 = 1.
  • Page 30 Preliminary W77E516 RCAP2H: This register is used to capture the TH2 value when a timer 2 is configured in capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when timer 2 is configured in auto-reload mode.
  • Page 31 Preliminary W77E516 Continued MXT freq. (Hz) ETM3 ETM2 ETM1 EMT0 22.6M − 25M 25.1M − 27.5M 27.6M − 30M 30.1M − 32.5M 32.6M − 35M 35.1M − 37.5M 37.6M − 40M BUSY: CPU returns busy status. CPU will set this bit after write NVM bytes and clear it after finished writing action.
  • Page 32 Preliminary W77E516 OV: Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as a result of the previous operation, or vice-versa. F1: User Flag 1: General purpose flag that can be set or cleared by the user by software.
  • Page 33 Preliminary W77E516 Accumulator Bit: ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Mnemonic: ACC Address: E0h ACC.7 − 0: The A (or ACC) register is the standard 8052 accumulator. Extended Interrupt Enable Bit: EWDI Mnemonic: EIE Address: E8h EIE.7 − 5: Reserved bits, will read high EWDI: Enable Watchdog timer interrupt EX5: External Interrupt 5 Enable.

  • Page 34: Instruction

    4 clock periods, while in the standard 8032 it consists of 12 clock periods. Also, in the W77E516 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can be two fetches per machine cycle, which works out to 6 clocks per fetch.
  • Page 35 Preliminary W77E516 Table 3. Instruction Timing for W77E516, continued W77E516 W77E516 W77E516 8032 Instruction Bytes Machine Clock Clock Op-Code 8032 Speed Cycles Cycles Cycles Ratio ADD A, R6 ADD A, R7 ADD A, @R0 ADD A, @R1 ADD A, direct...
  • Page 36 Preliminary W77E516 Table 3. Instruction Timing for W77E516, continued W77E516 W77E516 W77E516 8032 Instruction Bytes Machine Clock Clock Op-Code 8032 Speed Cycles Cycles Cycles Ratio CJNE A, #data, rel CJNE @R0, #data, rel CJNE @R1, #data, rel CJNE R0, #data, rel...
  • Page 37 Preliminary W77E516 Table 3. Instruction Timing for W77E516, continued W77E516 W77E516 W77E516 8032 Instruction Bytes Machine Clock Clock Op-Code 8032 Speed Cycles Cycles Cycles Ratio DJNZ R4, rel DJNZ R6, rel DJNZ R7, rel DJNZ direct, rel INC A INC R0...
  • Page 38 Preliminary W77E516 Table 3. Instruction Timing for W77E516, continued W77E516 W77E516 W77E516 8032 Instruction Bytes Machine Clock Clock Op-Code 8032 Speed Cycles Cycles Cycles Ratio MOV A, direct MOV A, #data MOV R0, A MOV R1, A MOV R2, A...
  • Page 39 Preliminary W77E516 Table 3. Instruction Timing for W77E516, continued W77E516 W77E516 W77E516 8032 Instruction Bytes Machine Clock Clock Op-Code 8032 Speed Cycles Cycles Cycles Ratio MOV direct, R4 MOV direct, R5 MOV direct, R6 MOV direct, R7 MOV direct, @R0...
  • Page 40 Preliminary W77E516 Table 3. Instruction Timing for W77E516, continued W77E516 W77E516 W77E516 8032 Instruction Bytes Machine Clock Clock Op-Code 8032 Speed Cycles Cycles Cycles Ratio RETI RL A RLC A RR A RRC A SETB C SETB bit SWAP A...

  • Page 41: Instruction Timing

    Hence it is important that the duty cycle of the clock be as close to 50% as possible to avoid timing conflicts. As mentioned earlier, the W77E516 does one op-code fetch per machine cycle. Therefore, in most of the instructions, the number of machine cycles needed to execute the instruction is equal to the number of bytes in the instruction.
  • Page 42 Preliminary W77E516 Single Cycle PSEN A7-0 Data_ in D7-0 AD7-0 PORT 2 Address A15-8 Figure 3. Single Cycle Instruction Timing Operand Fetch Instruction Fetch PSEN OP-CODE AD7-0 PC+1 OPERAND Address A15-8 Address A15-8 PORT 2 Figure 4. Two Cycle Instruction Timing...
  • Page 43 Preliminary W77E516 Instruction Fetch Operand Fetch Operand Fetch Operand Fetch PSEN A7-0 OP-CODE A7-0 A7-0 A7-0 AD7-0 OPERAND OPERAND OPERAND Port 2 Address A15-8 Address A15-8 Address A15-8 Address A15-8 Figure 6. Four Cycle Instruction Timing Operand Fetch Instruction Fetch...
  • Page 44 SFR. In the MOVX @DPTR type, the full 16-bit address is supplied by the Data Pointer. Since the W77E516 has two Data Pointers, DPTR and DPTR1, the user has to select between the two by setting or clearing the DPS bit. The Data Pointer Select bit (DPS) is the LSB of the DPS SFR, which exists at location 86h.
  • Page 45 Clock cycles in standard 8032= ((10 + (26 *50)) * 12 = (10 + 1300) * 12 = 15720 Clock cycles in W77E516 = ((10 + (26 * 50)) * 4 = (10 + 1300) * 4 = 5240 Block Move with Two Data Pointers in W77E516: ;...
  • Page 46 Preliminary W77E516 from 0 to 7, resulting in MOVX instructions that last from 2 to 9 machine cycles in length. Note that the stretching of the instruction only results in the elongation of the MOVX instruction, as if the state of the CPU was held for the desired period.
  • Page 47 Preliminary W77E516 Last Cycle First Second Third Next Instruction Machine Cycle of Previous Machine Cycle Machine Cycle Machine Cycle Instruction MOVX instruction cycle PSEN A0-A7 D0-D7 A0-A7 D0-D7 A0-A7 D0-D7 A0-A7 D0-D7 PORT 0 MOVX Inst. Next Inst. MOVX Data...
  • Page 48 Preliminary W77E516 Wait State Control Signal Either with the software using stretch value to change the required machine cycle of MOVX instruction, the W77E516 provides another hardware signal WAIT to implement the wider duration of external data access timing. This wait state control signal is the alternate function of P4.0 such that it can only be invoked to 44-pin PLCC/QFP package type.

  • Page 49: Power Management

    Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out. When the W77E516 is exiting from an Idle mode with a reset, the instruction following the one which put the device into Idle mode is not executed. So there is no danger of unexpected writes.
  • Page 50 The port pins output the values held by their respective SFRs. The W77E516 will exit the Power Down mode with a reset or by an external interrupt pin enabled as level detect. An external reset can be used to exit the Power down state. The high on RST pin terminates the Power Down mode, and restarts the clock.

  • Page 51: Reset Conditions

    Data Reset Conditions The user has several hardware related options for placing the W77E516 into reset condition. In general, most register bits go to their reset value irrespective of the reset condition, but there are a few flags whose state depends on the source of reset. The user can use these flags to determine the cause of reset using software.

  • Page 52: Reset State

    Preliminary W77E516 Reset State Most of the SFRs and registers on the device will go to the same condition in the reset state. The Program Counter is forced to 0000h and is held there as long as the reset condition is applied.

  • Page 53: Interrupts

    EWT bit. Interrupts The W77E516 has a two priority level interrupt structure with 12 interrupt sources. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or disabled.
  • Page 54 Preliminary W77E516 All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to disable all the interrupts, except PFI, at once.
  • Page 55 Preliminary W77E516 The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate service routine. This may or may not clear the flag which caused the interrupt. In case of Timer interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the appropriate timer service routine.

  • Page 56: Programmable Timers/Counters

    The maximum response time (if no other interrupt is in service) occurs if the W77E516 is performing a write to IE, IP, EIE or EIP and then executes a MUL or DIV instruction. From the time an interrupt source is activated, the longest reaction time is 12 machine cycles.

  • Page 57: Time-Base Selection

    8051 family, counting at the rate of 1/12 of the clock speed. This will ensure that timing loops on the W77E516 and the standard 8051 can be matched. This is the default mode of operation of the W77E516 timers. The user also has the option to count in the turbo mode, where the timers will increment at the rate of 1/4 clock speed.
  • Page 58 Preliminary W77E516 Mode 1 Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13 bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer moves from a count of FFFFh to 0000h.

  • Page 59: Timer/Counter 2

    Preliminary W77E516 While its basic functionality is maintained, it no longer has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a timer/counter and retains the use of GATE and INT1 pin.
  • Page 60 Preliminary W77E516 be set, which will also generate an interrupt. Setting the T2CR bit (T2MOD.3), the W77E516 allows hardware to reset timer 2 automatically after the value of TL2 and TH2 have been captured. T2M = CKCON.5 Clock Source Mode input C/T2 = T2CON.1...
  • Page 61 Preliminary W77E516 Auto-reload Mode, Counting Up/Down Timer/Counter 2 will be in auto-reload mode as an up/down counter if CP/ RL2 bit in T2CON is cleared and the DCEN bit in T2MOD is set. In this mode, Timer/Counter 2 is an up/down counter whose direction is controlled by the T2EX pin.

  • Page 62: Watchdog Timer

    Preliminary W77E516 Programmable Clock-out Timer 2 is equipped with a new clock-out feature which outputs a 50% duty cycle clock on P1.0. It can be invoked as a programmable clock generator. To configure Timer 2 with clock-out mode, software must initiate it by setting bit T2OE = 1, C/T2 = 0 and CP/RL = 0. Setting bit TR2 will start the timer.
  • Page 63 Preliminary W77E516 The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a known state. The RWT bit is used to restart the watchdog timer. This bit is self clearing, i.e. after writing a 1 to this bit the software will automatically clear it. The watchdog timer will now count clock cycles.

  • Page 64: Serial Port

    Serial Port Serial port in the W77E516 is a full duplex port. The W77E516 provides the user with additional features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports are capable of synchronous as well as asynchronous communication.
  • Page 65 The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the W77E516 and the device at the other end of the line. Any instruction that causes a write to SBUF will start the transmission.
  • Page 66 Preliminary W77E516 stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will be at the 10th rollover of the divide by 16 counter after a write to SBUF.
  • Page 67 Preliminary W77E516 Mode 2 This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a programmable 9th bit (TB8) and a stop bit (1). The 9th bit received is put into RB8. The baud rate is programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in PCON SFR.
  • Page 68 Preliminary W77E516 Clock Source Mode input div. by 4 osc/2 div. by 64 osc/32 div. by 1024 osc/512 Internal STOP PARIN Data Bus Write to ÷2 SOUT START SBUF LOAD SMOD= CLOCK (SMOD_1) TX START Transmit Shift Register SHIFT ÷16...
  • Page 69 Preliminary W77E516 Mode 3 This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user must first initialize the Serial related SFR SCON before any communication can take place. This involves selection of the Mode and baud rate. The Timer 1 should also be initialized if modes 1 and 3 are used.

  • Page 70: Framing Error Detection

    A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data communication. Typically the frame error is due to noise and contention on the serial communication line. The W77E516 has the facility to detect such framing errors and set a flag which can be checked by software.

  • Page 71: Timed Access Protection

    Watchdog control bits resulting in incorrect operation and loss of control. In order to prevent this, the W77E516 has a protection scheme which controls the write access to critical bits. This protection scheme is done using a timed access.

  • Page 72: Absolute Maximum Ratings

    Preliminary W77E516 TA, #055h 3 M/C WDCON, #00h 3 M/C Example 2: Valid access TA, #0AAh 3 M/C TA, #055h 3 M/C 1 M/C SETB EWT 2 M/C Example 3: Invalid access TA, #0AAh 3 M/C TA, #055h 3 M/C...
  • Page 73 Preliminary W77E516 11. DC CHARACTERISTICS −V = 5V ±10%, T = 25°C, Fosc = 20 MHz, unless otherwise specified.) SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT Operating Voltage No load Operating Current = RST = 5.5V Idle mode Idle Current IDLE = 5.5V...

  • Page 74: Ac Characteristics

    Preliminary W77E516 11. AC CHARACTERISTICS CLCL CLCH CLCX CHCL CHCX External Clock Characteristics PARAMETER SYMBOL MIN. TYP. MAX. UNITS NOTES Clock High Time 12.5 CHCX Clock Low Time 12.5 CLCX Clock Rise Time CLCH Clock Fall Time CHCL Note: Duty cycle is 50 %.

  • Page 75: Movx Characteristics Using Strech Memory Cycles

    Preliminary W77E516 MOVX Characteristics Using Strech Memory Cycles VARIABLE VARIABLE PARAMETER SYM. CLOCK CLOCK UNITS STRECH MIN. MAX. 1.5 t CLCL Data Access ALE Pulse Width LLHL2 2.0 t > 0 CLCL Address Hold After ALE Low for 0.5 t...

  • Page 76: Timing Waveforms

    Preliminary W77E516 MOVX Cycles 2 machine cycles 3 machine cycles CLCL 4 machine cycles CLCL 5 machine cycles 12 t CLCL 6 machine cycles 16 t CLCL 7 machine cycles 20 t CLCL 8 machine cycles 24 t CLCL 9 machine cycles...

  • Page 77: Data Memory Read Cycle

    Preliminary W77E516 Timing Waveforms, continued Data Memory Read Cycle LLDV WHLH LLWL PSEN RLRH LLAX1 RLDV AVLL RHDZ RLAZ AVWL1 RHDX PORT 0 INSTRUCTION ADDRESS DATA ADDRESS A0-A7 A0-A7 AVDV1 AVDV2 ADDRESS A8-A15 PORT 2 Data Memory Write Cycle WHLH...

  • Page 78: Typical Application Circuits

    Preliminary W77E516 13. TYPICAL APPLICATION CIRCUITS Expanded External Program Memory and Crystal P0.0 P0.1 P0.2 XTAL1 10 u P0.3 P0.4 XTAL2 P0.5 CRYSTAL P0.6 P0.7 8.2 K P2.0 P2.1 INT0 P2.2 INT1 P2.3 74F373 P2.4 P2.5 P2.6 P2.7 P1.0 P1.1 P1.2...

  • Page 79: Expanded External Data Memory And Oscillator

    Preliminary W77E516 Typical Application Circuits, continued Expanded External Data Memory and Oscillator Q0 2 P0.0 Q1 5 P0.1 Q2 6 P0.2 XTAL1 Q3 9 10 u P0.3 OSCILLATOR Q4 12 P0.4 Q5 15 XTAL2 P0.5 Q6 16 P0.6 8.2 K Q7 19 P0.7...

  • Page 80: 44-Pin Plcc

    Preliminary W77E516 Package Dimensions, continued 44-pin PLCC Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. 0.185 4.699 0.020 0.508 0.145 0.150 0.155 3.683 3.81 3.937 0.026 0.028 0.032 0.66 0.711 0.813 0.022 0.406 0.559 0.016 0.018...

  • Page 81: Application Note

    15. APPLICATION NOTE In-system Programming Software Examples This application note illustrates the in-system programmability of the Winbond W77E516 MTP-ROM microcontroller. In this example, microcontroller will boot from 64 KB APROM bank and waiting for a key to enter in-system programming mode for re-programming the contents of 64 KB APROM.
  • Page 82 Preliminary W77E516 SFRCN,#30H TCON,#00H ; TR = 0 TIMER0 STOP IP, #00H ; IP = 00H IE, #82H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE R6, #F0H ; TL0 = F0H R7, #FFH ; TH0 = FFH TL0, R6...
  • Page 83 Preliminary W77E516 TA, #AAH TA, #55H CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING. TCON, #00H ; TCON = 00H, TR = 0 TIMER0 STOP TMOD, #01H ; TMOD = 01H, SET TIMER0 A 16BIT TIMER IP, #00H ; IP = 00H IE, #82H ;...
  • Page 84 Preliminary W77E516 BLANK_CHECK_ERROR: ;******************************************************************************* ;* RE-PROGRAMMING 64KB APROM BANK ;******************************************************************************* PROGRAM_64KROM: R2, #00H ; TARGET LOW BYTE ADDRESS R1, #00H ; TARGET HIGH BYTE ADDRESS DPTR, #0H SFRAH, R1 ; SFRAH, TARGET HIGH ADDRESS SFRCN, #21H ; SFRCN = 21H, PROGRAM 64K APROM0 ;...
  • Page 85 ; IF ERROR OCCURS, REPEAT 3 TIMES. ; IN-SYST PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. 2727 North First Street, San Jose, 27F, 2299 Yan An W. Rd. Shanghai, No. 4, Creation Rd. III, Science-Based Industrial Park, CA 95134, U.S.A.

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