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Table of Contents-
1.
GENERAL DESCRIPTION ......................................................................................................................3
2.
FEATURES .............................................................................................................................................3
3.
PIN CONFIGURATION............................................................................................................................5
4.
PIN DESCRIPTION .................................................................................................................................6
5.
FUNCTIONAL DESCRIPTION ................................................................................................................8
5.1
Program Counter (PC)..............................................................................................................8
5.2
Stack Register (STACK)...........................................................................................................8
5.3
Program Memory (ROM) ..........................................................................................................9
5.3.1
5.3.2
5.4
Data Memory (RAM)...............................................................................................................12
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5
Accumulator (ACC).................................................................................................................16
5.6
Arithmetic and Logic Unit (ALU) .............................................................................................16
5.7
Main Oscillator........................................................................................................................16
5.8
Sub-oscillator..........................................................................................................................17
5.9
Dividers...................................................................................................................................17
5.10
Dual-clock Operation ..............................................................................................................17
5.11
Watchdog Timer (WDT) .........................................................................................................18
5.12
Timer/Counter.........................................................................................................................19
5.12.1
5.12.2
5.12.3
5.12.4
5.13
Interrupts ................................................................................................................................22
5.14
Stop Mode Operation .............................................................................................................24
5.14.1
5.15
Hold Mode Operation .............................................................................................................24
5.15.1
ROM Page Register (ROMPR) .........................................................................................10
ROM Addressing Mode ....................................................................................................10
Architecture ......................................................................................................................12
RAM Page Register (PAGE).............................................................................................12
WR Page Register (WRP)................................................................................................13
Data Bank Register (DBKRH, DBKRL).............................................................................14
RAM Addressing Mode.....................................................................................................15
Timer 0 (TM0) .................................................................................................................19
Timer 1 (TM1) .................................................................................................................20
Mode Register 0 (MR0) ..................................................................................................22
Mode Register 1 (MR1) ..................................................................................................22
Stop Mode Wake-up Enable Flag for RC and RD Port (SEF) ........................................24
Hold Mode Release Enable Flag (HEF, HEFD)..............................................................26
4-BIT MICROCONTROLLER
- 1 -
W742E/C813
Revision A1
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Summary of Contents for Winbond W742C813
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Page 1: Table Of Contents
W742E/C813 4-BIT MICROCONTROLLER Table of Contents- GENERAL DESCRIPTION ........................3 FEATURES .............................3 PIN CONFIGURATION..........................5 PIN DESCRIPTION ..........................6 FUNCTIONAL DESCRIPTION ........................8 Program Counter (PC)......................8 Stack Register (STACK)......................8 Program Memory (ROM) ......................9 5.3.1 ROM Page Register (ROMPR) ..................10 5.3.2 ROM Addressing Mode ....................10 Data Memory (RAM).......................12 5.4.1 Architecture ........................12... - Page 2 W742E/C813 5.15.2 Interrupt Enable Flag (IEF) .....................26 5.15.3 Port Enable Flag (PEF, P1EF)..................27 5.15.4 Hold Mode Release Condition Flag (HCF, HCFD) ............27 5.15.5 Event Flag (EVF, EVFD)....................28 5.16 Reset Function ........................28 5.17 Input/Output Ports RA, RB & P0.....................29 5.17.1 Port Mode 0 Register (PM0) ...................30 5.17.2 Port Mode 1 Register (PM1) ...................30 5.17.3...
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Page 3: General Description
W742E/C813 1. GENERAL DESCRIPTION The W742E/C813 (W742C813 is mask type, W742E813 is electrical erasable EPROM type) is a high- performance 4-bit microcontroller (µC) that built in 640-dot LCD driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers in dual-clock operation, a 40 × 16 LCD driver, ten 4-bit I/O ports (including 2 output port for LED driving), multiple frequency output, and one channel DTMF generator. - Page 4 W742E/C813 • Eleven interrupt sources − Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1) − Seven external interrupts (RC.0-3, P1.2 ( INT0 ), Serial Port, P1.3 ( INT1 )) • LCD driver output − 40 segments x 16 commons −...
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Page 5: Pin Configuration
W742E/C813 3. PIN CONFIGURATION S E G 1 0 S E G 3 1 S E G 0 9 (K0.0) S E G 3 2 S E G 0 8 (K0.1) S E G 3 3 S E G 0 7 (K0.2) S E G 3 4 (K0.3) -
Page 6: Pin Description
W742E/C813 4. PIN DESCRIPTION SYMBOL FUNCTION XIN2 Input pin for sub-oscillator. Connected to 32.768 KHz crystal only. XOUT2 Output pin for sub-oscillator with internal oscillation capacitor. Connected to 32.768 KHz crystal only. XIN1 Input pin for main-oscillator. Connected to 3.58 MHz crystal or resistor to generate system clock. XOUT1 Output pin for main-oscillator. - Page 7 W742E/C813 Pin Description, continued SYMBOL FUNCTION System reset pin with internal pull-high resistor. : supply programming voltage, without internal pull-high resistor for electrical erasable EPROM type for avoiding high voltage programming damage LCD segment output pins. SEG0−SEG31 LCD common signal output pins. COM0−COM15 The LCD alternating frequency can be selected by code option.
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Page 8: Functional Description
W742E/C813 5. FUNCTIONAL DESCRIPTION 5.1 Program Counter (PC) Organized as an 15-bit binary counter (PC0 to PC14), the program counter generates the addresses of the 32768(32K) × 16 on-chip ROM containing the program instruction words. When the interrupt or initial reset conditions are to be executed, the corresponding address will be loaded into the program counter directly. -
Page 9: Program Memory (Rom)
W742E/C813 5.3 Program Memory (ROM) The read-only memory (ROM) is used to store program codes or the look-up table that can be arranged up to 65536(64K) × 4 bits. The program ROM is divided into sixteen pages; the size of each page is 2048(2K) ×... -
Page 10: Rom Page Register (Rompr)
W742E/C813 5.3.1 ROM Page Register (ROMPR) The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows: ROMPR Note: W means write only. Bit 3, Bit 2, Bit 1, Bit 0 ROM page bits: 0000 = ROM page 0 (0000H - 07FFH) 1000 = ROM page 8 (4000H - 47FFH) 0001 = ROM page 1 (0800H - 0FFFH) - Page 11 W742E/C813 3. Conditional JMP Bit 14-0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 jmp into the same page Example: Lable_A0 Lable_A1 Lable_A2 Lable_A3 Label_Az Label_Anz Label_Ac Label_Anc 4. Look-up Table Bit 15-0 15 14 13 12 11 10 (PC-4000H)*4 TA33 TA32 TA31 TA30 TA23 TA22 TA21 TA20 TA13 TA12 TA11 TA10 TA03 TA02 TA01 TA00 Look-up table address = (PC address - 4000H) *4...
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Page 12: Data Memory (Ram)
W742E/C813 5.4 Data Memory (RAM) 5.4.1 Architecture The static data memory (RAM) used to store data is arranged up to 5120(5K) × 4 bits. The data RAM is divided into 40 banks; each bank has 128 × 4 bits. Executing the MOV DBKRL,WR, MOV DBKRH,WR or MOV DBKRL,#I, MOV DBKRH,#I instructions can determine which data bank is used. -
Page 13: Wr Page Register (Wrp)
W742E/C813 Bit 3 is reserved. Bit 2, Bit 1, Bit 0 RAM page bits: 000 = Page 0 (00H - 0FH) 001 = Page 1 (10H - 1FH) 010 = Page 2 (20H - 2FH) 011 = Page 3 (30H - 3FH) 100 = Page 4 (40H - 4FH) 101 = Page 5 (50H - 5FH) 110 = Page 6 (60H - 6FH) -
Page 14: Data Bank Register (Dbkrh, Dbkrl)
W742E/C813 5.4.4 Data Bank Register (DBKRH, DBKRL) The data bank register is organized as two 4-bit binary register. The bit descriptions are as follows: DBKRL DBKRH Note: R/W means read/write available. Bit5, Bit 4, Bit3, Bit 2, Bit 1, Bit 0 Data memory bank bits: 000000 = Data bank 0 (000H - 07FH) 000001 = Data bank 1 (080H - 0FFH) 000010 = Data bank 2 (100H - 17FH) -
Page 15: Ram Addressing Mode
W742E/C813 011011 = Data bank 27 (0D80H - 0DFFH) 011100 = Data bank 28 (0E00H - 0E7FH) 011101 = Data bank 29 (0E80H - 0EFFH) 011110 = Data bank 30 (0F00H - 0F7FH) 011111 = Data bank 31 (0F80H - 0FFFH) 100000 = Data bank 32 (1000H - 107FH) 100001 = Data bank 33 (1080H - 10FFH) 100010 = Data bank 34 (1100H - 117FH) -
Page 16: Accumulator (Acc)
W742E/C813 3. Indirect Addressing Bit 12-0 RAM addr BH1 BH0 BL3 BL2 BL1 BL0 DP2 DP1 DP0 (WA3 WA2 WA1 WA0) (WA0-3) is Working register contents ; DP0-3 is RAM page register(PAGE) BL0-3 is DBKRL register ; BH0-1 is DBKRH register Example: DBKRL,BL_value ;... -
Page 17: Sub-Oscillator
W742E/C813 5.8 Sub-oscillator The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the 32768 Hz crystal could be connected to XIN2 and XOUT2. 5.9 Dividers Divider 0 is organized with a 14-bit binary up-counter that is designed to generate periodic interrupt. When the main clock starts action, the Divider0 is incremented by each clock (F ). -
Page 18: Watchdog Timer (Wdt)
W742E/C813 We must remember that the X010B state is inhibitive, because it will induce the system shutdown. The organization of the dual-clock operation mode is shown in Figure 5-4. HOLD SCR.0 XIN1 Main Oscillator Fosc System Clock XOUT1 Generator SCR.1 enable/disable STOP Divider 0... -
Page 19: Timer/Counter
W742E/C813 Divider0 HEF.0 Hold mode release (HCF.0) EVF.0 Fosc IEF.0 Q10 Q11 Q12 Divider interrupt 1. Reset 2. CLR EVF,#01H Option code is reset to "0" 3. CLR DIVR0 Disable SCR.2 Fosc/16384 Overflow signal Qw1 Qw2 System Reset Fosc/2048 Enable 1. -
Page 20: Timer 1 (Tm1)
W742E/C813 1. Reset 2. CLR EVF,#02H 3. Reset MR0.3 to 0 4.MOV TM0L,R or MOV TM0H,R Disable MR0.0 HEF.1 Fosc/1024 8-Bit Binary Hold mode release (HCF.1) Down Counter IEF.1 Fosc/4 (Timer 0) EVF.1 Timer 0 interrupt (INT1) Enable Set MR0.3 to 1 MOV TM0H,R MOV TM0L,R 1. - Page 21 W742E/C813 M O V T M 1 H , R M O V T M 1 L , R EVF.7 MR1.3 1. Reset Auto-reload buffer 2. INT7 accept MR1.1 3. CLR EVF, #80H 8 bits Underflow signal 4. Set MR1.3 to 1 Enable 8-Bit Binary Fosc/64...
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Page 22: Mode Register 0 (Mr0)
W742E/C813 5.12.3 Mode Register 0 (MR0) Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows: Note: W means write only. Bit 0 = 0 The fundamental frequency of Timer 0 is F The fundamental frequency of Timer 0 is F... - Page 23 W742E/C813 by executing the DIS INT instruction. When an interrupt is generated in the hold mode, the hold mode will be released momentarily and interrupt service routine will be executed. After executing interrupt service routine, the µC will enter hold mode automatically. The operation flow chart is shown in Figure 5-9.
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Page 24: Stop Mode Operation
W742E/C813 5.14 Stop Mode Operation In stop mode, all operations of the µC cease. The µC enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a falling signal on the RC or RD port). - Page 25 W742E/C813 Divider 0, Divider 1, Timer 0, Timer 1, Signal Change at RC,RD port, falling edge at P1.2,P1.3, Serial I/O HOLD Mode? Interrupt Interrupt Enable? Enable? Flag Set? Flag Set? Reset EVF Flag Reset EVF Flag Execute Execute Interrupt Service Routine Interrupt Service Routine Flag Set? (Note)
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Page 26: Hold Mode Release Enable Flag (Hef, Hefd)
W742E/C813 5.15.1 Hold Mode Release Enable Flag (HEF, HEFD) The hold mode release enable flag is organized on an 8-bit binary register (HEF.0 to HEF.7) and a 1- bit register (HEFD). The HEF and HEFD are used to control the hold mode release conditions. It is controlled by the MOV HEF, #I, MOV HEFD,#I instructions. -
Page 27: Port Enable Flag (Pef, P1Ef)
W742E/C813 5.15.3 Port Enable Flag (PEF, P1EF) The port enable flag is organized as 8-bit binary register (PEF.0 to PEF.7) and 4-bit register (P1EF.2 and P1EF.3). Before port RC, RD may be used to release the hold mode, the content of the PEF must be set first. -
Page 28: Event Flag (Evf, Evfd)
W742E/C813 HCF.0 = 1 Hold mode was released by overflow from the divider 0. HCF.1 = 1 Hold mode was released by underflow from the timer 0. HCF.2 = 1 Hold mode was released by a signal change at port RC. HCF.3 = 1 Hold mode was released by a signal change at port P1.2 ( INT0 ). -
Page 29: Input/Output Ports Ra, Rb & P0
W742E/C813 Table 3 The initial state after the reset function is executed Program Counter (PC) 000H TM0, TM1 Reset MR0, MR1, PAGE Registers Reset PSR0, PSR1, PSR2, SCR Registers Reset IEF, HEF, HEFD, HCF, PEF, P1EF, EVF, EVFD, SEF flags Reset WRP, DBKR Register Reset... -
Page 30: Port Mode 0 Register (Pm0)
W742E/C813 Input/Output Pin of the P0 I/O PIN Output Buffer P0.n DATA Enable PM6.n MOV P0,R instruction Enable MOVA R,P0 instruction Figure 5-11 Architecture of P0 Input/Output pins 5.17.1 Port Mode 0 Register (PM0) The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the port structure;... -
Page 31: Port Mode 2 Register (Pm2)
W742E/C813 Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin Bit 3 = 0 RA.3 works as output pin;... -
Page 32: Serial I/O Interface
W742E/C813 5.18 Serial I/O interface The bit 0 and bit 1 of port P0 can be used as a serial input/output port. P0.0 is the serial clock I/O pin and P0.1 is the serial data I/O pin. A 4-bit binary register, Serial Interface Control register (SIC), controls the serial port. - Page 33 W742E/C813 SIP R Ins. P0.0 rising latch P0.0 falling latch Data latch BUSYI (PSR2.1) EVF5 P0.1 NOTE: The serial clock frequency is fosc/2 Figure 5-12 Timing of the Serial Input Function (SIP R) (2) When the SOP R instruction is executed, the data will be loaded to the serial output buffer (SOB) from ACC and the RAM, the low nibble data of SOB is from ACC register and the high nibble data is from RAM, and bit 3 of port status register 2(PSR2) will be set to "1"...
- Page 34 W742E/C813 SOP R Ins. P0.0 data changed at falling edge P0.0 data changed at rising edge Data latch BUSYO (PSR2.3) EVF5 P0.1 NOTE: The serial clock frequency is fosc/2 Figure 5-13 Timing of the Serial Output Function (SOP R) Port Status Register 2 (PSR2) Port status register 2 is organized as 4-bit binary register (PSR2.0 to PSR2.3).
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Page 35: Input Ports Rc
W742E/C813 5.19 Input Ports RC Port RC consists of pins RC.0 to RC.3. Each pin of port RC can be connected to a pull-high resistor, which is controlled by the port mode 0 register (PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the specified pins of port RC will execute the hold mode release or interrupt subroutine. -
Page 36: Port Status Register 0 (Psr0)
W742E/C813 5.19.1 Port Status Register 0 (PSR0) Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows: PSR0 Note: R means read only. -
Page 37: Port Status Register 1 (Psr1)
W742E/C813 DATA BUS PM0.3 PEF.4 PSR1.0 Signal change detector RD.0 HEFD EVFD PM0.3 PEF.5 HCFD PSR1.1 Signal change detector RD.1 PM0.3 PEF.6 PSR1.2 Signal change CLR EVFD detector RD.2 Reset PM0.3 PEF.7 PSR1.3 Signal change detector RD.3 Reset MOV PEF, #I CLR PSR1 SEF.4 Falling... -
Page 38: Output Port Re & Rf
W742E/C813 Bit 0 = 1 Signal change at RD.0 Bit 1 = 1 Signal change at RD.1 Bit 2 = 1 Signal change at RD.2 Bit 3 = 1 Signal change at RD.3 5.21 Output Port RE & RF Output port RE and RF are used as output of the internal RT port. When the MOV RE, R or MOV RF, R instruction is executed, the data in the RAM will be output to port RT through port RE or RF. -
Page 39: Dtmf Register
W742E/C813 5.23.1 DTMF Register DTMF register is organized as 4-bit binary register. By controlling the DTMF register, one tone of the low/high group can be selected. The MOV DTMF,R instruction can specify the wanted tones. The bit descriptions are as follows: DTMF Note: W means write only. - Page 40 W742E/C813 8 Hz, 4 Hz, 2 Hz, or 1 Hz (the clock source is from 32.768 KHz crystal). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown in next page.
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Page 41: Lcd Controller/Driver
W742E/C813 5.25 LCD Controller/Driver The W742E/C813 can directly drive an LCD with 40 segment output pins and 16 common output pins for a total of 40 × 16 dots. The LCD driving mode is 1/5 bias 1/8 or 1/16 duty. The alternating frequency of the LCD can be set as Fw/16, Fw/32, Fw/64, or Fw/128. -
Page 42: Lcd Ram Addressing Method
W742E/C813 Table 6 The reation between the LCDR and segment/common pins used as LCD drive output pins OUTPUT COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 BIT3 BIT2 BIT1 BIT0 BIT3 BIT2 BIT1 BIT0 SEG0 LCDR01 LCDR00 SEG1 LCDR03 LCDR02 SEG38 LCDR4D LCDR4C... - Page 43 W742E/C813 outside chip inside chip VLCD1 Internal VLCD2 Circuit VLCD S T O P L C D O F F Code Option Note: VR is determined by LCDCC register Figure 5-18 LCD power control circuit LCDCC Note: W means write only. LCDCC VLCD/VLCD2 0000H...
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Page 44: Seg32-Seg39 Using As Dc Output (Nmos Open Drain Type)
W742E/C813 5.25.3 SEG32-SEG39 Using as DC Output (NMOS open drain type) SEG32−SEG39 pins output type can be changed to DC output mode by code mask option. The correspoinding control resigters are LCD RAM address LCDR40 and LCDR41, these two parts are individually enabled by code mask option. -
Page 45: Absolute Maximum Ratings
= 25° C, LCD on, INTERNAL PUMP DISABLE; unless otherwise specified) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT OP. Voltage (W742C813) Op. Voltage (W742E813) Op. Current (Crystal type) No load (Ext-V) In dual-clock normal operation Op. Current (Crystal type) No load (Ext-V) µA... -
Page 46: Ac Characteristics
W742E/C813 DC Characteristics, continued PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Input Low Voltage 0.3 V Input High Voltage 0.7 V MFP Output Low Voltage = 3.5 mA MFP Output High Voltage = 3.5 mA Port RA, RB, RD Output = 2.0 mA Low Voltage Port RA, RB, RD Output... -
Page 47: Instruction Set Table
W742E/C813 9. INSTRUCTION SET TABLE Symbol Description ACC: Accumulator ACC.n: Accumulator bit n Working Register WRP: WR Page register PAGE: Page Register DBKRL: Data Bank Register (Low nibble) DBKRH: Data Bank Register (High nibble) ROMPR: ROM Page Register MR0: Mode Register 0 MR1: Mode Register 1 PM0:... - Page 48 W742E/C813 Continued TM0L: Low nibble of the Timer 0 counter TM0H: High nibble of the Timer 0 counter TM1L: Low nibble of the Timer 1 counter TM1H: High nibble of the Timer 1 counter LCDCC LCD contrast control register TAB0: Look-up table address buffer 0 TAB1: Look-up table address buffer 1...
- Page 49 W742E/C813 Machine code Mnemonic Function Flag affected Arithmetic ← 0001 1000 0xxx xxxx R, ACC ZF, CF (R) + (ACC) 0001 1100 i i i i nnnn ← WRn, #I ZF, CF (WRn) + I 0001 1001 0xxx xxxx ← ADDR R, ACC ZF, CF...
- Page 50 W742E/C813 Instruction set, continued Machine code Mnemonic Function Flag affected Branch 0111 0 ← aaa aaaa aaaa PC14~PC0 (ROMPR)×800H+L10~L0 1000 0 ← aaa aaaa aaaa PC10~PC0 L10~L0; if ACC.0 = "1" 1001 0 ← aaa aaaa aaaa PC10~PC0 L10~L0; if ACC.1 = "1" 1010 0 ←...
- Page 51 W742E/C813 Instruction set, continued Machine code Mnemonic Function Flag affected Data move ← 1110 1nnn nxxx xxxx WRn, R 1111 1nnn nxxx xxxx ← R, WRn (WRn) 0110 1nnn nxxx xxxx ← MOVA WRn, R ACC, WRn ← 0111 1nnn nxxx xxxx MOVA R, WRn ACC, R...
- Page 52 W742E/C813 Instruction set, continued Machine code Mnemonic Function Flag affected Flag & Register 0101 1111 1xxx xxxx ← MOVA R, PAGE ACC, R PAGE (Page Register) ← 0101 1110 1xxx xxxx PAGE, R PAGE ← 0101 0110 1000 0i i i PAGE, #I PAGE ←...
- Page 53 W742E/C813 Instruction set, continued Machine code Mnemonic Function Flag affected Flag & Register 0101 1101 0xxx xxxx MOVA R, EVFL ACC, R← EVF.0 - EVF.3 0101 1101 1xxx xxxx MOVA R, EVFH ACC, R← EVF.4 - EVF.7 0100 0001 i i i i i i i i HEF, #I Set/Reset HOLD mode release Enable Flag 0011 0001 0000 000 i...
- Page 54 W742E/C813 Instruction set, continued Machine code Mnemonic Function Flag affected ← 1001 1000 0xxx xxxx LPL, R 1001 1000 1xxx xxxx ← LPH, R ← 1001 1010 0xxx xxxx @LP, R [(LPH)×10H+(LPL)] 1001 1011 0xxx xxxx ←[ R, @LP (LPH) ×10H+(LPL)] 0000 0010 0000 0000 LCDON LCD ON...
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Page 55: Package Dimensions
W742E/C813 10. PACKAGE DIMENSIONS 100L QFP (14 x 20 x 2.75 mm footprint 4.8 mm) θ See Detail F Seating Plane Controlling dimension: Millimeters D i m e n s i o n i n i n c h D i m e n s i o n i n m m Symbol Min. - Page 56 W742E/C813 Winbond Electronics (H.K.) Ltd. Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Winbond Electronics North America Corp. Headquarters Headquarters Winbond Memory Lab. Winbond Memory Lab. Unit 9-15, 22F, Millennium City, Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No.
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