Power integrations LinkSwitch-4 LNK4*15D Series Application Note page 21

AN-69
Step 14 – PCB Layout Guidelines
Good layout practice helps with:
Achieving low EMI
•
Good ESD immunity
•
Thermal optimization
•
Design for manufacture
•
Some simple, good practices and guidelines for routing are:
Make track widths appropriate for current to be carried
•
Space tracks according to voltage difference between them
•
Keep tracks as short as possible.
•
Prioritize critical paths: highest first (high current, high frequency,
•
high-voltage)
Keep thin tracks away from board edge
•
Route tracks to center of a connecting pad
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Functional Considerations
Loops (signal paths and ground returns) that carry fast edges are a
potential source of radiated EMI. The faster and larger the current
fluctuations, the higher the radiated EMI power will be. Also the
larger the area enclosed by the loop, the higher the level of EMI. The
latter is where good PCB design can help, and poor design can cause
a real problem. The key is to keep current loops small and run out/
return tracks close together. Doing so keeps the loop area and
radiated emissions down.
Critical Connections
The track between the feedback resistor R
•
GROUND pins must be as short as possible to avoid poor perfor-
mance. C recharge currents and primary current out of the
VCC
Figure 28. Star Point Ground Connections.
www.power.com
and LinkSwitch-4
FB2
High current loops
– minimize area to
reduce radiated
emissions
c
VCC1
R
CS2
CS
C
IN
R
CS
GROUND pin must not generate volt drops in the GND tracking
that interfere with voltage on the FEEDBACK pin due to the GND
connection of R .
FB2
The impedance driving the FEEDBACK pin is quite high. As a
•
result, the FEEDBACK pin waveform can easily be distorted by
parasitic capacitive coupling from the primary BJT switch. When
laying out the PCB, it is important to minimize stray capacitance
between the switch and feedback node. This can be achieved by
placing the R and R
FB1 FB2
making the FB node small in area.
The tracks between the BJT base and emitter to the BD and ED
•
pins of the IC must be as short as possible to avoid poor EMI
performance.
The tracks between the transformer and BJT collector must be as
•
short as possible and the total area as small as possible. If there
is a primary clamp circuit, the diode anode should connect to the
collector, not the resistor R
The current sense resistor R
•
the required rated current. The connections should be as small as
possible and the track as wide as possible. The R
small and any track resistance will affect the operation of the
power supply. There should be dedicated tracks between R
both C and R . Highlighted nodes in Figure 29.
IN2 CS2
Mount R very close to the CS pin of the IC.
•
CS2
Having a star point at the ground of the IC to all grounded
•
components will help EMC and circuit performance, see Figure 28.
Note that the bias wind, D
loop, then its GND is connected to the star point.
VCC
R
FB1
FB
GND R
FB2
PI-8182-111016
Application Note
resistors adjacent to the FEEDBACK pin,
, to minimize the high dv/dt node area.
C1
programs the power supply giving it
CS
resistance is
CS
and C form their own close small
BIAS VCC2
D
BIAS
C
VCC2
and
CS
21
Rev. B 10/17