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SUPPLEMENTAL MATERIAL
DIMM and CPU Layout
Memory is organized as shown in
Figure 8
UCS B420 M4 Memory Organization
40
Figure
A3
A2
A1
Channel A
B3
B2
B1
Channel B
C3
C2
C1
Channel C
D3
D2
D1
Channel D
CPU 1
I3
I2
I1
Channel I
CPU 3
J3
J2
J1
Channel J
K2
K1
K3
Channel K
I3
I2
I1
Channel L
48 DIMMS
4 memory channels per CPU
3 DIMMs per channel
8.
E1 E2
Channel E
F1 F2
Channel F
G1 G2
Channel G
H1 H2
Channel H
CPU 2
M1 M2
Channel M
CPU 4
N1 N2
Channel N
O1 O2
Channel O
P1 P2
Channel P
E3
F3
G3
H3
M3
N3
O3
P3
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