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Artesyn ATCA-7480 Installation And Use Manual

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ATCA-7480
Installation and Use
P/N: 6806800T17A
February 2015

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Summary of Contents for Artesyn ATCA-7480

  • Page 1 ATCA-7480 Installation and Use P/N: 6806800T17A February 2015...
  • Page 2 Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes.

  • Page 3: Table Of Contents

    Ethernet Connector ..........68 ATCA-7480 Installation and Use (6806800T17A)
  • Page 4 4.20 SMBus ................95 ATCA-7480 Installation and Use (6806800T17A)
  • Page 5 5.1.12.7 IPMC Watchdog Timeout Register ........144 ATCA-7480 Installation and Use (6806800T17A)
  • Page 6 5.1.30 Scratch Registers............171 ATCA-7480 Installation and Use (6806800T17A)
  • Page 7 7.3.1 Using Standard IPMI Commands ..........224 ATCA-7480 Installation and Use (6806800T17A)
  • Page 8 PICMG 3.0 Commands ............. 250 Artesyn Embedded Technologies Specific Commands ....... . . 252 8.3.1 Serial Output Commands .
  • Page 9 9.3.9 Payload Power Failure State Sensor..........307 ATCA-7480 Installation and Use (6806800T17A)
  • Page 10 Related Documentation ............. . 327 Artesyn Embedded Technologies - Embedded Computing Documentation ....327 Manufacturers’...
  • Page 11 Power Requirements ............48 Table 2-4 Power Consumption of ATCA-7480 with and without RTM ......48 Table 2-5 Switch SW1 settings .
  • Page 12 Power Status Register ............139 ATCA-7480 Installation and Use (6806800T17A)
  • Page 13 CPU Presence Detection Register ..........164 ATCA-7480 Installation and Use (6806800T17A)
  • Page 14 Logged Error Events ............210 ATCA-7480 Installation and Use (6806800T17A)
  • Page 15 Set Debug Level Command Description ......... . 266 ATCA-7480 Installation and Use (6806800T17A)
  • Page 16 Artesyn MAC Address Descriptor ........
  • Page 17 Block Diagram ATCA-7480 ........
  • Page 18 IPMC block diagram of ATCA-7480 ........

  • Page 19: About This Manual

    IPMI Feature Set on page 279, provides information about controlling via IPMI.  Replacing the Battery on page 323, provides the battery exchange procedures.  Related Documentation on page 327, provides links to further blade-related  documentation. ATCA-7480 Installation and Use (6806800T17A)
  • Page 20 Industry Standard Architecture Media Access Control NEBS Network Equipment Building System NVRAM Nonvolatile Random Access Memory Original Equipment Manufacturer Out-Of-Service Printed Circuit Board Peripheral Component Interconnect Power Entry Module PICMG PCI Industrial Computer Manufacturers Group ATCA-7480 Installation and Use (6806800T17A)
  • Page 21 0 through F), for example used for addresses and offsets 0b0000 Same for binary numbers (digits are 0 and 1) bold Used to emphasize a word Used for on-screen output and code related elements Screen or commands in body text ATCA-7480 Installation and Use (6806800T17A)
  • Page 22 Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered. Pay attention to important information ATCA-7480 Installation and Use (6806800T17A)
  • Page 23 About this Manual Summary of Changes Part Number Publication Date Description 6806800T17A February 2015 Initial Version ATCA-7480 Installation and Use (6806800T17A)
  • Page 24 About this Manual About this Manual ATCA-7480 Installation and Use (6806800T17A)

  • Page 25: Safety Notes

    The blade has been tested in a standard Artesyn Embedded Technologies system and found to comply with the limits for a Class A digital device in this system, pursuant to part 15 of the FCC Rules, EN 55022 Class A respectively.
  • Page 26 Damage of Blade and Additional Devices and Modules Incorrect installation of additional devices or modules may damage the blade or the additional devices or modules. Before installing or removing an additional device or module, read the respective documentation ATCA-7480 Installation and Use (6806800T17A)
  • Page 27 When operating the blade, make sure that forced air cooling is available in the shelf. When operating the blade in areas of electromagnetic radiation ensure that the blade is bolted on the system and the system is shielded by enclosure. Injuries or Short Circuits Blade or power supply ATCA-7480 Installation and Use (6806800T17A)
  • Page 28 The EMI radiation compliancy of the product has been qualified in a reference system with 10 ATCA-7480 boards installed each with the Spread Spectrum feature enabled. Please note that the integrator needs to verify the EMI radiation compliancy of other configurations/settings (for example, Spread Spectrum disabled).
  • Page 29 Safety Notes Environment Always dispose of used blades, system components and RTMs according to your country’s legislation and manufacturer’s instructions. ATCA-7480 Installation and Use (6806800T17A)
  • Page 30 Safety Notes ATCA-7480 Installation and Use (6806800T17A)

  • Page 31: Sicherheitshinweise

    Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am Produkt durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur bitte an die für Sie zuständige Geschäftsstelle von Artesyn Embedded Technologies. So stellen Sie sicher, dass alle sicherheitsrelevanten Aspekte beachtet werden.
  • Page 32 Sicherheitshinweise Das Blade wurde in einem Artesyn Embedded Technologies Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Blades in Gewerbe- sowie...
  • Page 33 Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Blades können zu Kurzschlüssen führen. Betreiben Sie das Blade nur innerhalb der angegebenen Grenzwerte für die relative Luftfeuchtigkeit und Temperatur. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf dem Blade kein Kondensat befindet. ATCA-7480 Installation and Use (6806800T17A)
  • Page 34 Prüfen Sie deshalb immer, ob die Leitung spannungsfrei ist, bevor Sie Ihre Arbeit fortsetzen, um Schäden oder Verletzungen zu vermeiden. Die Messung der EMV Abstrahlung wurde in einem Referenzsystem mit 10 ATCA-7480 Boards ermittelt, bei denen die "Spread Spectrum" Funktion eingeschalten war. Der Integrator ist dafür verantwortlich, daß...
  • Page 35 Verwenden Sie deshalb nur den Batterietyp, der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung. Umweltschutz Entsorgen Sie alte Batterien und/oder Blades/Systemkomponenten/RTMs stets gemäß der in Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers. ATCA-7480 Installation and Use (6806800T17A)
  • Page 36 Sicherheitshinweise ATCA-7480 Installation and Use (6806800T17A)

  • Page 37: Introduction

    Chapter 1 Introduction Features The ATCA-7480 is a high-performance ATCA compliant single board computer designed for demanding storage and processing applications. The main features of the ATCA-7480 board are as follows: Designed for NEBS level 3  Dual socket Intel Xeon E5-2600 V3 (Haswell-EP socket LGA2011-3) ...

  • Page 38: Mechanical Data

    322.25 mm +0/-0.3mm Length 280 mm +0/-0.3 mm Thickness 2.4 mm + 0.2mm Mounting height top side 21.33 mm (component side 1) Mounting height bottom side 1.61 mm (component side 2) Weight ATCA-7480-0GB(-L): 3.5kg ATCA-7480-0GB-H: 3.6kg ATCA-7480 Installation and Use (6806800T17A)

  • Page 39: Product Identification

    The following figure shows the location of the serial number label. Figure 1-1 Serial Number Location Serial Number J11 DIMM 1 ZONE 1 Ordering Information The ATCA-7480 is a high performance ATCA compliant single board computer designed for demanding storage and processing applications. ATCA-7480 Installation and Use (6806800T17A)

  • Page 40: Table 1-2 Blade Variants

    Introduction The following table lists the blade variants that are available upon release of this publication. Consult your local Artesyn Embedded Technologies sales representative for the availability of other variants. Table 1-2 Blade Variants Product Name Description ATCA-7480-0GB ATCA-7480 Blade with Dual Intel Xeon E5-2648L V3 12-Core @1.8GHz processors (Haswell-EP 75W TDP), 2.5MB per Core Last Level Cache,...

  • Page 41: Figure 1-2 Declaration Of Conformity

    Introduction The following figure is a copy of Declaration of Conformity for ATCA-7480. Figure 1-2 Declaration of Conformity ATCA-7480 Installation and Use (6806800T17A)
  • Page 42 Introduction ATCA-7480 Installation and Use (6806800T17A)

  • Page 43: Hardware Preparation And Installation

    Environmental and Power Requirements In order to meet the environmental requirements, the blade has to be tested in the system in which it is to be installed. ATCA-7480 Installation and Use (6806800T17A)

  • Page 44: Environmental Requirements

    Blade Overheating and Blade Damage Operating the blade without forced air cooling may lead to blade overheating and thus blade damage. When operating the blade, make sure that forced air cooling is available in the shelf. ATCA-7480 Installation and Use (6806800T17A)

  • Page 45: Table 2-1 Environmental Requirements

    Random 20-200Hz at 3 m Shock Half-sine, 11 ms, 30 m/s Blade level packaging Half-sine, 6 ms at 180 m/s Free Fall 1.2 m/ packaged (according to ETSI 300 019-2-2) 100 mm unpackaged (according to Telcordia GR-63-core) ATCA-7480 Installation and Use (6806800T17A)

  • Page 46: Figure 2-1 Location Of Critical Temperature Spots (Blade Top Side)

    Exact locations of critical temperature spots: 1. On the PIM (U34) (On top of the transformer). Maximum up to 90 2. On the 48V/12V DC/DC (U35) (on the PCB, next to the transformer). Maximum up to ATCA-7480 Installation and Use (6806800T17A)

  • Page 47: Power Requirements

    In the following table you will find typical examples of power requirements with and without accessories installed. For information on the accessories' power requirements, refer to the documentation delivered together with the respective accessory or consult your local Artesyn Embedded Technologies representative for further details. ATCA-7480 Installation and Use (6806800T17A)

  • Page 48: Table 2-3 Power Requirements

    The following table provides information about the maximum power consumption of ATCA- 7480 all variants equipped with DIMIs, SSDs, and RTM-ATCA-748x-40G including 4x QSFP. The table also contains power consumption details of blade without any RTM. Table 2-4 Power Consumption of ATCA-7480 with and without RTM Max. Power Typ. Power...
  • Page 49 There is also a dependency on the batch variance of the major components like the processor and DIMMs used. Hence, Artesyn does not represent or warrant that measurement results of a specific board provide guaranteed maximum values for a series of boards.

  • Page 50: Blade Layout

    Hardware Preparation and Installation Blade Layout The following figure shows the location of components on the ATCA-7480: Figure 2-2 ATCA-7480 Blade Layout J28 DIMM 8 J27 DIMM 7 J26 DIMM 6 J25 DIMM 5 J21 DIMM 1 RTM 12V Power...

  • Page 51: Switch Settings

    BIOS Image Swap Default Image ON=secondary Image in 16MB device SW1.3 TSOP or Debug-Socket SPI Boot Boot from BIOS select Socket OFF= Boot from TSOP SPI Flash (either Default/Recovery) ON = Boot from Debug Socket SPI Flash ATCA-7480 Installation and Use (6806800T17A)

  • Page 52: Table 2-6 Switch Sw2 Settings

    SW3.2 controls Boot flash select if SW3.1 is ON OFF = Boot from "Default SPI Boot Flash" device OFF = Boot from "Default SPI Boot Flash" device ON= Boot from "Recovery SPI Boot Flash" device ATCA-7480 Installation and Use (6806800T17A)

  • Page 53: Installing The Blade Accessories

    DIMM memory modules in order to match the main memory size to your needs. The corresponding installation/removal procedures are described in this section. For the location of the DIMM Memory modules, see Figure "ATCA-7480 Blade Layout" on page ATCA-7480 Installation and Use (6806800T17A)

  • Page 54: Table 2-8 Dimm Sockets

    DIMM configuration is recommended; that is, every memory channel using the same type and amount of DIMMs. In case of using only one DIMM per channel, make sure that you use only primary sockets and leave the secondary sockets empty. ATCA-7480 Installation and Use (6806800T17A)
  • Page 55 Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life. Before touching the module or electronic components, make sure that you are working in an ESD-safe environment. ATCA-7480 Installation and Use (6806800T17A)

  • Page 56: Ssd Carrier And Mo297 Ssd Modules

    SSDs and the MO297-A compliant SSDs. The SD module is an accessory kit and is not part of the default ATCA-7480. The following procedure describes the steps to install/remove the MO297-A compliant SSD module.
  • Page 57 3. Fasten the SSD module to the blade using the screws supplied with the ACC kit. 4. Reinstall the blade into the system as described in Installing and Removing the Blade on page The additional resource (either memory or SATA SSD) will be detected automatically during the boot-up sequence. ATCA-7480 Installation and Use (6806800T17A)

  • Page 58: Installing And Removing The Blade

    4. Reinstall the blade into the system as described in Installing and Removing the Blade on page Installing and Removing the Blade The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelves. ATCA-7480 Installation and Use (6806800T17A)

  • Page 59: Installing The Blade

    The following procedure describes the installation of the blade. It assumes that your system is powered on. If your system is not powered on, you can disregard the blue LED and skip the respective step. In this case, it is purely a mechanical installation. ATCA-7480 Installation and Use (6806800T17A)
  • Page 60 Latch Handle 2. Slide the latch into the release position and pull out the handle outward to unlatch the handle from the faceplate. Do not rotate the handle fully outward. ATCA-7480 Installation and Use (6806800T17A)
  • Page 61 If your shelf is powered, as soon as the blade is connected to the backplane power pins, the blue LED is illuminated. ATCA-7480 Installation and Use (6806800T17A)

  • Page 62: Removing The Blade

    Before touching the blade or electronic components, make sure that you are working in an ESD-safe environment. Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning. When plugging the blade in or removing it, do not press on the faceplate, instead use the handles. ATCA-7480 Installation and Use (6806800T17A)
  • Page 63 Wait until the blue LED is permanently illuminated before removing the blade. 3. Remove the faceplate cables, if applicable. 4. Loosen the screws of the faceplate until the blade is detached from the shelf. 5. Remove the blade from the shelf. ATCA-7480 Installation and Use (6806800T17A)
  • Page 64 Hardware Preparation and Installation ATCA-7480 Installation and Use (6806800T17A)

  • Page 65: Controls, Indicators, And Connectors

    Chapter 3 Controls, Indicators, and Connectors Faceplate The following figure illustrates the connectors, keys, and LEDs available on the faceplate: Figure 3-1 Faceplate ATCA-7480 Installation and Use (6806800T17A)

  • Page 66: Leds

    Green: Link is available Off: No link Activity (lower) Yellow: Activity Off: No activity U1, U2 Base interface activity is visualized via FPGA LEDs U1 and U2 User LED, selectable color via FPGA register. Colors: Red, Green, Amber ATCA-7480 Installation and Use (6806800T17A)

  • Page 67: Keys

    On pressing it, a hard reset is triggered and all attached on-board devices are reset. You cannot reset the IPMC via this key. 3.1.3 Connectors The blade provides the following connectors at its faceplate: 2x Ethernet  1x Serial  2x USB 3.0/USB 2.0  ATCA-7480 Installation and Use (6806800T17A)

  • Page 68: Serial Com#1 P17

    3.1.3.1 Serial COM#1 P17 Serial line interface #1 of Glue Logic FPGA is available at the faceplate of ATCA-7480. A female RJ45 connector is used for serial line connection. The pinout in the following table is used according to the Cisco-like Pinout. Additionally, Hardware Handshake support signals are available.

  • Page 69: Serial Interface Connector

    SW2-1 also changes the serial connector that you need to access to make use of the serial redirection feature. The pinout of the serial interface connector is shown below. Figure 3-3 Serial Interface Connector Pinout ATCA-7480 Installation and Use (6806800T17A)

  • Page 70: Usb 3.0 Connectors

    Figure 3-4 USB Connector Pinout Attaching a device to the front panel USB ports that exceeds the maximum USB current rating of 500mA per port will result in the ATCA-7480 protecting itself through a controlled board shutdown. On-board Connectors The blade provides the following on-board connectors: MO297 SSD module carrier connector ...

  • Page 71: Figure 3-5 Location Of Mo297 Ssd Module Connector

    Controls, Indicators, and Connectors The location of the MO297 SSD module carrier/riser is illustrated in the following figure. Figure 3-5 Location of MO297 SSD Module Connector MO-297 Carrier J11 DIMM 1 ZONE 1 ATCA-7480 Installation and Use (6806800T17A)

  • Page 72: Table 3-3 Signal Segment Pinout

    Table 3-3 Signal Segment Pinout Pin Number Function Description mate Differential singal Pair A mate Differential signal Pair B mate Table 3-4 Power Segment Pinout Pin Number Function Not used (3.3V) Not used (3.3V) Not used (3.3V Pre- Charge) ATCA-7480 Installation and Use (6806800T17A)
  • Page 73 Controls, Indicators, and Connectors Table 3-4 Power Segment Pinout (continued) Pin Number Function 5V Pre-Charge RESERVED Not used (12V Pre- Charge) Not used (12V) Not used (12V) ATCA-7480 Installation and Use (6806800T17A)

  • Page 74: Advancedtca Backplane Connectors

    AdvancedTCA standard, and are called P10, P20 and P23, P30, P31 and P32. The pinouts of all these connectors are given in this section. Figure 3-7 Location of AdvancedTCA Connectors J11 DIMM 1 ZONE 1 ATCA-7480 Installation and Use (6806800T17A)

  • Page 75: Figure 3-8 P10 Backplane Connector Pinout

    Reserved signals  Figure 3-8 P10 Backplane Connector Pinout Zone 2 contains the two connectors P20 and P23. They carry the following types of signals: Telecom clock signals (CLKx_)  Base interface signals (BASE_)  ATCA-7480 Installation and Use (6806800T17A)

  • Page 76: Figure 3-9 P20 Backplane Connector Pinout - Rows A To D

    In all other cases the pins are unconnected and consequently marked as "n.c.". The pinouts of P20 and P23 are as follows. Figure 3-9 P20 Backplane Connector Pinout - Rows A to D ATCA-7480 Installation and Use (6806800T17A)

  • Page 77: Figure 3-10 P20 Backplane Connector Pinout - Rows E To H

    Controls, Indicators, and Connectors Figure 3-10 P20 Backplane Connector Pinout - Rows E to H Figure 3-11 P23 Backplane Connector Pinout - Rows A to D ATCA-7480 Installation and Use (6806800T17A)

  • Page 78: Figure 3-12 P23 Backplane Connector Pinout - Rows E To H

    Zone 3 contains the three connectors P30, P31, and P32. They are used to connect an RTM to the blade and carry the following signals: Serial (RS232_x_yyyy)  Serial ATA (SATAx_yyy)  USB (USBxy)  PCI Express (PCIEx_yyy)  IPMI (IPMB1_xxx, ISMB_xxx)  Power (VP12_RTM, V3P3_RTM, VP5_RTM)  ATCA-7480 Installation and Use (6806800T17A)

  • Page 79: Figure 3-13 P30 Backplane Connector Pinout - Rows A To D

    Controls, Indicators, and Connectors SAS Update channels  General control signals (BD_PRESENTx, RTM_PRSNT_N, RTM_RST_KEY-, RTM_RST-)  Figure 3-13 P30 Backplane Connector Pinout - Rows A to D Figure 3-14 P30 Backplane Connector Pinout - Rows E to H ATCA-7480 Installation and Use (6806800T17A)

  • Page 80: Figure 3-15 P31 Backplane Connector Pinout - Rows A To D

    P31 Backplane Connector Pinout - Rows E to H PCIE_CPU1_P3_RX_N<1> PCIE_CPU1_P3_RX_P<1> PCIE_CPU1_P3_TX_P<1> PCIE_CPU1_P3_TX_N<1> PCIE_CPU1_P3_RX_N<3> PCIE_CPU1_P3_RX_P<3> PCIE_CPU1_P3_TX_P<3> PCIE_CPU1_P3_TX_N<3> PCIE_CPU1_P3_RX_N<5> PCIE_CPU1_P3_RX_P<5> PCIE_CPU1_P3_TX_P<5> PCIE_CPU1_P3_TX_N<5> PCIE_CPU1_P3_RX_N<7> PCIE_CPU1_P3_RX_P<7> PCIE_CPU1_P3_TX_P<7> PCIE_CPU1_P3_TX_N<7> PCIE_CPU1_P3_RX_N<9> PCIE_CPU1_P3_RX_P<9> PCIE_CPU1_P3_TX_P<9> PCIE_CPU1_P3_TX_N<9> PCIE_CPU1_P3_RX_N<11> PCIE_CPU1_P3_RX_P<11> PCIE_CPU1_P3_TX_P<11> PCIE_CPU1_P3_TX_N<11> PCIE_CPU1_P3_RX_N<13> PCIE_CPU1_P3_RX_P<13> PCIE_CPU1_P3_TX_P<13> PCIE_CPU1_P3_TX_N<13> PCIE_CPU1_P3_RX_N<15> PCIE_CPU1_P3_RX_P<15> PCIE_CPU1_P3_TX_P<15> PCIE_CPU1_P3_TX_N<15> n.c. ATCA-7480 Installation and Use (6806800T17A)

  • Page 81: Figure 3-17 P32 Backplane Connector Pinout - Rows A To D

    Controls, Indicators, and Connectors Figure 3-17 P32 Backplane Connector Pinout - Rows A to D Figure 3-18 P32 Backplane Connector Pinout - Rows E to H ATCA-7480 Installation and Use (6806800T17A)
  • Page 82 Controls, Indicators, and Connectors ATCA-7480 Installation and Use (6806800T17A)

  • Page 83: Functional Description

    Block Diagram ATCA-7480 Processor ATCA-7480 provides two Intel Xeon E5-26xxL V3 (Haswell-EP) server processors as the central processing unit (CPU). Each processor provides 40 PCIe lanes up to Gen3 speeds (8GT/s). The processors are connected with each other through 2 Intel QuickPath Interconnect point-to- point links capable of up to 9.8 GT/s.

  • Page 84: Ddr4 Main Memory

    RAS features supported with ECC (mirroring, x8/x4 SDDC, Sparing, Scrubbing)  Memory Error signaling for uncorrectable errors  Memory Error signaling for correctable memory errors  ADR feature to support persistent memory structures in DDR3 (asynchronous DRAM  refresh) ATCA-7480 Installation and Use (6806800T17A)

  • Page 85: Platform Controller Hub (Pch) Intel C612 Wellsburg

    SPI Interface (Boot Flash)  LPC/KCS Interface  Up to 10 serial ATA (SATA) controllers 6Gb/s of which four are used on ATCA-7480  Six USB 3.0 and 8 PCIe 2.0 interfaces of which 2+2 are used on ATCA-7480 ...

  • Page 86: Intel I350 Quad Gb Ethernet Controller

    Recovery BIOS Flash (SPI 1)  The flash is allocated for storing the binary code of the BIOS. The ATCA-7480 boots from the primary flash SPI 0 under normal circumstances. If booting BIOS from primary flash SPI 0 fails, a hardware mechanism automatically changes the flash device select logic to boot from the recovery flash SPI 1.

  • Page 87: Storage Controller

    Intel Wellsburg PCH via a SATA interface. The modular approach consists of a riser card, which provide up to three sockets for SSDs and the MO297-A compliant SSDs. Before the storage solution can be mounted on ATCA-7480, the riser card and the SSDs have to be pre- mounted.

  • Page 88: Ipmc

    Functional Description 4.10 IPMC ATCA-7480 contains the IPMC building block from Pigeon Point Systems (PPS). It is based on Microsemi Smartfusion cSOC (customizable System-on-Chip). The PPS IPMC controller is based on 32-bit Cortex M3 microcontroller operating at 50 MHz. The PPS implementation is the BMR-A2F200-AMCc-CM288R utilizing Microsemi Smartfusion A2F200M3F-CSG288I device.

  • Page 89: I2C Bus

    Functional Description 4.10.1 I2C Bus ATCA-7480 contains the IPMC controller Master-Only I2C Bus. It is also called as Private I2C Bus, which is connected to a FRU EEPROM, temperature sensors, and monitoring logic of the PIM. Figure 4-2 Master Only I2C Bus Architecture...

  • Page 90: Fru Data Serial Idrom

    Maste-Only I2C 4.10.2 FRU Data serial IDROM ATCA-7480 contains a 64KByte IDROM. It contains the FRU data, and board specific information. For example, serial number of the board, MAC addresses of network interfaces, and some additional information. The EEPROM has an I2C interface and is connected to the on- board Private I2C interface of IPMC building block.

  • Page 91: System Event Log Eeprom

    Functional Description 4.10.3 System Event Log EEPROM ATCA-7480 contains a 64KByte System Event Log (SEL) PROM. The EEPROM has an I2C interface and is connected to the on-board Private I2C interface of IPMC building block. The IDROM is assigned to I2C address 0xA2.

  • Page 92: Control Logic

    4.15 Faceplate Serial Interfaces The ATCA-7480 has two serial interfaces. They are fully compliant to industry standard 16550 asynchronous communication controllers. The two Serial line interfaces #1 and #2 are integrated in the Intel DH8900CC PCH and routed to the on-board FPGA, which distributes them to either Faceplate, RTM, or IPMC for SOL.

  • Page 93: Ipmc Debug Console

    The IPMC Debug Console IF connection is normally routed to a 3-pin on-board header (RS232) The IPMC Debug monitor terminal output can also be routed to the Faceplate. The IPMC Debug Console is also available when the ATCA-7480 Payload is powered off. Table 4-3 IPMC Debug Console Destination Selection SW2.2...

  • Page 94: Usb 3.0 Interfaces

    The ATCA-7480 provides an on-board Infineon SLB9635TT1.2 FW3.16 TPM Controller connected to the LPC bus of PCH. This advanced Infineon controller guarantees that ATCA- 7480 is fully compliant to TPM 1.2 specification. ATCA-7480 is ready to migrate to TPM 2.0. ATCA-7480 Installation and Use (6806800T17A)

  • Page 95: Real Time Clock

     provides 300 hours of RTC/SRAM backup. 4.20 SMBus Intel C612 PCH (Wellsburg) provides six SMBus interfaces. Only four interfaces are used on ATCA-7480 as described in the following table: Table 4-4 SMBus Interface Device / SMBus Description Intel C612...

  • Page 96: Figure 4-3 Smbus Architecture

    Functional Description The following figure shows the ATCA-7480 SMBus architecture. Figure 4-3 SMBus Architecture DB 1900 Ret#1 Ret#2 Fab#1 Fab#2 isol isol LM75 Upper LM75 Lower PCH SMBUS 4300 (MGMT Domain) SMLINK1 Wellsburg SMLINK0 4300 IPMB-L The following table provides SMBus mapping address details.

  • Page 97: Table

    Wellsburg PCH Temp 48V Power PIM4328 ATCA-7480 Intel Interface Sensor Wellsburg PCH CB1900Z clock ATCA-7480 Intel buffer 9ZX21901BKLF Wellsburg PCH Retimer #1 IDT 89HT0816 ATCA-7480 Intel Wellsburg PCH Retimer #2 IDT 89HT0816 ATCA-7480 Intel Wellsburg PCH ATCA-7480 Installation and Use (6806800T17A)
  • Page 98 Functional Description ATCA-7480 Installation and Use (6806800T17A)

  • Page 99: Maps And Registers

    For example, LPC: r/w means that the register bit is readable/writable from the LPC interface IPMC: The prefix “IPMC:” signals that the access is restricted to the IPMC I2C interface. For example, IPMC: r/w means that the register bit is readable/writable from IPMC I2C interface ATCA-7480 Installation and Use (6806800T17A)

  • Page 100: Register Decoding

    All LPC I/O accesses to address POSTCODE and the address range REGISTERS and within the address ranges of COM1 or COM2 (only when enabled during Super IO configuration) are decoded by the LPC core. 5.1.1.1.2 LPC Memory Decoding The LPC interface never responds to LPC memory accesses. ATCA-7480 Installation and Use (6806800T17A)

  • Page 101: I2C Register Decoding

    The two 7 segment LED displays are also used for power failure indication. Table 5-5 POST Code Register LPC I/O Address: 0x80 IPMC I2C Address: 0x7f Description Default Access POST codes from host LPC: r/w IPMC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 102: Super Io Configuration Register

    2. Write 86H to Configuration Index Port. 5.1.3.2 Existing the Configuration State The device exits the Configuration State by the following contiguous sequence: 1. Write 68H to Configuration Index Port. 2. Write 08H to Configuration Index Port. ATCA-7480 Installation and Use (6806800T17A)

  • Page 103: Configuration Mode

    The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode. Table 5-8 Global Configuration Register Summary Index Address Description 0x07 Super IO Logical Device Number ATCA-7480 Installation and Use (6806800T17A)

  • Page 104: Table 5-9 Super Io Logical Device Number Register

    Table 5-10 Super IO Device Identification Register Index Address: 0x20 Description Default Access Device ID LPC: r Table 5-11 Super IO Device Revision Register Index Address: 0x21 Description Default Access Device Revision 0x01 LPC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 105: Table 5-12 Super Io Lpc Control Register

    SERIRQ Mode: LPC: r 1: Continuous Mode UART Clock pre-divide LPC: r/w 00: divide by 1 01: divide by 8 10: divide by 26 (CLK_UART is 48 MHz) 11: reserved Reserved LPC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 106: Table 5-14 Logical Device Configuration Register Summary

    Table 5-15 Logical Device Enable Register Index Address: 0x30 Description Default Access Logical Device Enable: LPC: r/w 0: disabled. Currently selected device is inactive. 1: enabled. The currently selected device is enabled. Reserved LPC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 107: Table 5-18 Logical Device Common Decode Ranges

    Register 0x61is 0xF8. Table 5-18 below for Common Decode Ranges: Table 5-18 Logical Device Common Decode Ranges IO Address range Description 0x3F8 - 0x3FF COM1 0x2F8 - 0x2FF COM2 0x2E8 - 0x2EF COM3 0x3E8 - 0x3EF COM4 ATCA-7480 Installation and Use (6806800T17A)

  • Page 108: Table 5-19 Logical Device Primary Interrupt Register

    0-4 in the corresponding UART IER and the occurrence of the corresponding UART event (i.e. Modem Status Change, Receiver Line Error Condition, Transmit Data Request, Receiver Data Available or Receiver Time Out) and setting the OUT2 bit in the MCR. ATCA-7480 Installation and Use (6806800T17A)

  • Page 109: Uart1 And Uart2 Register Map

    The state of the Divisor Latch Bit (DLAB), which is the MOST significant bit of the Serial Line Control Register (SCR), affects the selection of certain of the UART registers. The DLAB bit must be set high by the system software to access the Baud Rate Generator Divisor Latches (DLL and DLM). ATCA-7480 Installation and Use (6806800T17A)

  • Page 110: Uart Registers Dlab=0

    FIFO. Table 5-24 Receiver Buffer Register (RBR) if DLAB=0 LPC IO Address: Base Description Default Access Receiver Buffer register (RBR) Undef. LPC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 111: Table 5-25 Transmitter Holding Register (Thr) If Dlab=0

    Transmitter holding register empty (THRE) interrupt LPC: r/w enable/disable 1: THRE interrupt enabled 0: THRE interrupt disabled Receiver line status interrupt enable/disable LPC: r/w 1: receiver line status interrupt enabled 0: receiver line status interrupt disabled ATCA-7480 Installation and Use (6806800T17A)

  • Page 112: Table 5-27 Uart Interrupt Priorities2

    Modem Status: one or more of the modem input signals has changed state Table 5-28 Interrupt Identification Register (IIIR) LPC IO Address: Base + 2 Description Default Access Interrupt status bit: LPC: r 1: no interrupt pending 0: interrupt pending ATCA-7480 Installation and Use (6806800T17A)

  • Page 113: Table 5-29 Interrupt Identification Register Decode

    0b1100 Character FIFO Mode only: At least 1 character is in Reading the Receiver FIFO or Timeout receiver FIFO and there was no activity for setting RESETRF bit in FCR indication. a time period. register ATCA-7480 Installation and Use (6806800T17A)

  • Page 114: Table 5-30 Fifo Control Register (Fcr)

    (bit is self-clearing) 0: No effect Transmit FIFO reset: LPC: w 1: Bytes in receiver FIFO and counter are reset. Shift register is not reset (bit is self-clearing) 0: No effect Receiver/Transmitter ready. Not supported. LPC: w ATCA-7480 Installation and Use (6806800T17A)

  • Page 115: Table 5-31 Line Control Register (Lcr)

    Stop bit length: LPC: r/w 1: 1.5 stop bits for 5 bit WORD length 1: 2 stop bits for 6, 7, and 8 bit WORD length 0: 1 stop bit for any serial character WORD length ATCA-7480 Installation and Use (6806800T17A)
  • Page 116 Bit 7 must be cleared during a read or write to access the RBR, THR, or IER.: 1: Access to DLL and DLM registers 0: Access to RBR, THR and IER registers ATCA-7480 Installation and Use (6806800T17A)

  • Page 117: Table 5-32 Modem Control Register (Mcr)

    Modem control inputs are disconnected Modem control outputs are internally connected to modem control inputs. Modem control outputs are forced to the inactive (high) levels: 1: Loop back mode activated 0: Normal operation ATCA-7480 Installation and Use (6806800T17A)
  • Page 118 LSR error bits are set and are not cleared until software reads LSR, even if the character in the FIFO is read and a new character is now at the top of the FIFO. ATCA-7480 Installation and Use (6806800T17A)

  • Page 119: Table 5-33 Line Status Register (Lsr)

    FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO: 1: Parity error occurred 0: No parity error ATCA-7480 Installation and Use (6806800T17A)
  • Page 120 THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO: 1: THR/Transmit FIFO empty 0: THR/Transmit FIFO contains data ATCA-7480 Installation and Use (6806800T17A)
  • Page 121 Modem Status Register provide change information. Bits 03:00 are set to a logic 1 when a control input from the Modem changes state. They are reset to a logic 0 when the processor reads the Modem Status Register. ATCA-7480 Installation and Use (6806800T17A)

  • Page 122: Table 5-34 Modem Status Register (Msr)

    1 (RTS#). Complement of the data set ready (DSR#) input Ext. LPC: r When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR#). ATCA-7480 Installation and Use (6806800T17A)

  • Page 123: Programmable Baud Rate Generator

    Upon loading either of the divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. Access to the divisor latch can be done with a word write. ATCA-7480 Installation and Use (6806800T17A)

  • Page 124: Table 5-36 Divisor Latch Lsb Register (Dll), If Dlab=1

    Description Default Access Divisor Latch LSB (DLL) Undef. LPC: r/w Table 5-37 Divisor Latch MSB Register (DLM), if DLAB=1 LPC IO Address: Base + 1 Description Default Access Divisor Latch MSB (DLM) Undef. LPC: r/w ATCA-7480 Installation and Use (6806800T17A)

  • Page 125: Fpga Register Mapping

    FPGA Version Register (See, Table 5-40) 0x03 Serial Redirection Control Register (See, Table 5-41) 0x04 Serial over LAN Control Register (See, Table 5-42) 0x05 Serial Line Routing Register (See, Table 5-43) 0x06 IPMC Power Level Register ATCA-7480 Installation and Use (6806800T17A)
  • Page 126 DIMM ADR Status Register (See, Table 5-61) 0x1E CPU Control Register (See, Table 5-62) 0x1F S-States Control Register (See, Table 5-63) 0x20 NMI Generation Register (See, Table 5-64) 0x20 r/w1c NMI Interrupt Status Register (See, Table 5-65) ATCA-7480 Installation and Use (6806800T17A)
  • Page 127 0x54 CPU Presence Detection Register (See, Table 5-88) 0x57 CPU Error Status Register (See, Table 5-89) 0x60 Telecom Clock Monitor Control Register (See, Table 5-90) 0x61 r/w1c Telecom Clock Monitor Status Register (See, Table 5-91) ATCA-7480 Installation and Use (6806800T17A)
  • Page 128 5-103) 0x7D LPC Scratch Register (See, Table 5-104) 0x7E IPMC Scratch Register (See, Table 5-105) 0x7F POST Code Register (See, Table 5-5) For LPC I/O address 0x80 is used. See Table 5-5 POST Code Register. ATCA-7480 Installation and Use (6806800T17A)

  • Page 129: Module Identification Register

    Maps and Registers 5.1.6 Module Identification Register The Module Identification Register identifies the ATCA-7480 blade. Table 5-39 Module Identification Register Address Offset: 0x00 Description Default Access 15:0 ATCA-7480 Blade Module Identification 0x7480 5.1.7 Version Register The version register provides the version of the FPGA bit stream. The initial value starts at 0x01 and will be incremented with each new release.

  • Page 130: Serial Over Lan (Sol) Control Register

    SOL over COM1 enable: PWR_GOOD: 0 IPMC: r/w 0: disabled LPC: r 1: enabled. COM1 is forwarded to IMPC SOL over COM2 enable: PWR_GOOD: 0 IPMC: r/w 0: disabled LPC: r 1: enabled. COM2 is forwarded to IMPC ATCA-7480 Installation and Use (6806800T17A)

  • Page 131: Serial Line Routing Register

    0: COM1 to Faceplate and COM2 to RTM LPC: r 1: COM1 to RTM and COM2 to Faceplate IPMC_COM_ROUTE_DEBUG PWR_GOOD:0 IPMC: r/w 0: IPMC Serial Debug Interface to 3 Pin Header LPC: r 1: IPMC Serial Debug Interface to Faceplate Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 132: Ipmc Power Failure Registers

    The table below shows all possible failing states and their coding. Table 5-45 ME Power Failure States State State Coding Name Description ME_OFF Timeout. ASW power good for more than 45ms also ME is in ME_OFF state. ME_ON: ASW power good lost ATCA-7480 Installation and Use (6806800T17A)

  • Page 133: Payload Power Failure Registers

    Note: Only valid when ME Failure (Bit 7) of ME Power Failure State Register (Table 5-47) is set. Reserved IPMC: r 5.1.11.2 Payload Power Failure Registers When a payload power failure occurs, the red power failure LED is switched ON (signal PWR_FAIL_ is driven low). ATCA-7480 Installation and Use (6806800T17A)

  • Page 134: Table 5-47 Payload Power Failure State Register

    Coding Name Description CLK_ENABLE One or more voltages have failed, which have been already enabled and sampled good. One or more voltages have failed, which have been already enabled and sampled good. Other cause: Thermtrip ATCA-7480 Installation and Use (6806800T17A)
  • Page 135 WAIT_100MS One or more voltages have failed, which have been already enabled and sampled good. WAKE_UP Timeout. Board does not wake up within 5s Other These values will never occur. ATCA-7480 Installation and Use (6806800T17A)

  • Page 136: Table 5-49 Payload Power Failure Cause Register 1

    12V power good failure (signal PWRGD_VP12): PWR_GOOD:0 IPMC: r 0: No 12V power issue. 1: 12V power failure. 5V aux power good failure (signal PWR_GOOD:0 IPMC: r PWRGD_VP5AUX): 0: No 5V aux power issue. 1: 5V aux power failure. ATCA-7480 Installation and Use (6806800T17A)

  • Page 137: Table 5-50 Payload Power Failure Cause Register 2

    1.8V power good failure (signal PWRGD_V1P8): PWR_GOOD:0 IPMC: r 0: No 1.8V power issue. 1: 1.8V power failure. 1.5V power good failure (signal PWRGD_V1P5): PWR_GOOD:0 IPMC: r 0: No 1.5V power issue. 1: 1.5V power failure. ATCA-7480 Installation and Use (6806800T17A)

  • Page 138: Table 5-51 Payload Power Failure Cause Register 3

    IPMC: r PWRGD_VTT_ABCD): 0: No VTT CPU0 power issue. 1: VTT CPU0 power failure. VTT CPU1 power good failure (signal PWR_GOOD:0 IPMC: r PWRGD_VTT_EFGH): 0: No VTT CPU1 power issue. 1: VTT CPU1 power failure. ATCA-7480 Installation and Use (6806800T17A)

  • Page 139: Power Status Register

    Status of signal SLP_S3_. Ext. IPMC: r Reserved IPMC: r Status of signal CPU_PWRGD Ext. IPMC: r Status of signal XDP_HOOK1_SEL Ext. IPMC: r Status of signal XDP_PWRGD_RST_ Ext. IPMC: r Status of signal XDP_CPU_SYSPWROK Ext. IPMC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 140: Reset Registers

    RTM_PB_RST_ Reset key at RTM PWR_GOOD:0 LPC: r/w1c 1: Reset occurred IPMC: r Reserved PCH_PLTRST_ reset PWR_GOOD:0 LPC: r/w1c 1: Reset occurred IPMC: r IPMC_RST_ REQ_ Payload Reset from IPMC. PWR_GOOD:0 LPC: r/w1c 1: Reset occurred IPMC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 141: Reset Mask Register

    When one of the IPMC Watchdog Timeout bit of IPMC Watchdog Timeout Register is set, the corresponding BIOS IPMC Watchdog Timeout bit is set. The BIOS clears this status bit by writing one. OS should never write to this register. ATCA-7480 Installation and Use (6806800T17A)

  • Page 142: Bios Push Button Enable Register

    IPMC reset. After a timeout of 8s, the resets are armed again. Table 5-56 BIOS Push Button Enable Register Address Offset: 0x13 Description Default Access BIOS Push Button Enable Register LPC: w ATCA-7480 Installation and Use (6806800T17A)

  • Page 143: Os Reset Source Register

    1: Reset occurred IPMC: r Reserved PCH_PLTRST_ reset PWR_GOOD:0 LPC: r/w1c 1: Reset occurred IPMC: r IPMC_RST_ REQ_ Payload Reset from IPMC. PWR_GOOD:0 LPC: r/w1c 1: Reset occurred IPMC: r 5.1.12.6 OS IPMC Watchdog Timeout Register ATCA-7480 Installation and Use (6806800T17A)

  • Page 144: Ipmc Watchdog Timeout Register

    IPMC Watchdog Timeout bit is set from low to high, the corresponding bits in Table 5-55 Table 5-58 are set. IPMC needs to clear the IPMC watchdog timeout bit to arm IPMC watchdog timeout event recognition. ATCA-7480 Installation and Use (6806800T17A)

  • Page 145: Ipmc Reset Source Register

    PWR_GOOD:1 IPMC: r/w1c 1: Reset occurred XDPx reset request (Any one of XDPx signal PWR_GOOD:0 IPMC: r/w1c caused reset 1: Reset occurred PB_RST_ face plate push button reset PWR_GOOD:0 IPMC: r/w1c 1: Reset occurred Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 146: Ipmc Interrupt Status Register

    IPMC version 1.2.0018 or higher is needed to clear the interrupt flag. Otherwise the IPMC interrupt will always be active and produce infinite IPMC interrupts. Table 5-61 IPMC Interrupt Status Register Address Offset: 0x19 Description Default Access IPMC interrupt status PWR_GOOD:0 IPMC: r/w1c 1: Platform Reset occurred (PCH_PLT_RST_) Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 147: 10Dimm Adr Configuration Register

    ADR enable for RTM Push button reset PWR_GOOD:0 LPC: r/w 1: ADR enabled IPMC: r 0: ADR disabled ADR enable for IPMI reset PWR_GOOD:0 LPC: r/w 1: ADR enabled IPMC: r 0: ADR disabled Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 148: 11Dimm Adr Status Register

    PCH_PSTATE_ pulse generation. Minimum low pulse width is Xμs IPMC: w 0: No action 1: Generate PSTATE low pulse. PCH_RCIN_ pulse generation. Minimum low pulse width is Xμs: IPMC: w 0: No action 1: Generate RCIN low pulse. Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 149: S-States Control Register

    Power Button Override Function. PWRBTN low pulse is 5s. IPMC: w 0: No action 1: Generate PWRBTN long low pulse. Forced transition to S5 Reserved 5.1.15 NMI Control Status Registers IPMC can initiate a NMI. Host can identify NMI comes from IPMC. ATCA-7480 Installation and Use (6806800T17A)

  • Page 150: Nmi Generation Register

    5.1.16 Interrupt Control and Status Registers The interrupt status registers indicate events of the interrupt input signals. When an interrupt event occurred, the corresponding status bit is read 1. Writing 1 of the corresponding bit clears the bit. ATCA-7480 Installation and Use (6806800T17A)

  • Page 151: Internal Interrupt Status Register

    Address Offset: 0x22 Description Default Access 3: 0 Telecom CLK_MONITOR_FINISHED interrupt: LPC: r One or more Telecom Clock measurements have finished. Telecom CLK_MONITOR_OUT_OF_RANGE interrupt: LPC: r One or more Telecom Clocks are out of range ATCA-7480 Installation and Use (6806800T17A)

  • Page 152: Telecom Interrupt Control Register

    RTM interrupt sources Ext. LPC: r 0: RTM_SPI_MISO is high. No RTM interrupt. 1: RTM_SPI_MISO is low. One or more RTM interrupt sources are active. When RTM SPI Master face is active the current level is latched. ATCA-7480 Installation and Use (6806800T17A)

  • Page 153: Interrupt Mask And Map Registers

    Table 5-72 Address Map of Interrupt Mask and Map Registers Address Offset of Interrupt Source(s) Description Interrupt Mask IPMC to Host IPMC signals interrupt 0x25 Interrupt Telecom Interrupt Telecom Interrupt. 0x26 RTM_SPI_MISO RTM interrupt sources 0x27 ATCA-7480 Installation and Use (6806800T17A)

  • Page 154: Table

    0x12: Frame number 18. INTA_ 0x13: Frame number 19. INTB_ 0x14: Frame number 20. INTC_ 0x15: Frame number 21. INTD_ 0x16 - 0x1F: Frame number 22-31. IRQ Frame Number not valid. Value is ignored. Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 155: Pci Express Hot Plug I2C Io Expander Registers

    Ext. Power LED on the baseboard. For a precise definition refer to PCI Express Base Specification, Revision 3.0. PWREN# Output Output signal allowing software to Ext. enable or disable power to a PCI Express slot. ATCA-7480 Installation and Use (6806800T17A)
  • Page 156 A retention latch is used on the platform to mechanically hold the card in place. Refer to PCI Express Server/Workstation Module Electromechanical Spec Rev 1.0 for details of the timing requirements of this pin output. ATCA-7480 Installation and Use (6806800T17A)

  • Page 157: Pca9555 Internal Register Access

    The flash status register indicates the actual status of the mechanical switches SW1.3 (Signal BOOT_TSOP), SW3.1 (Signal BOOT_SEL_EN_) and SW3.2 (Signal BOOT_DEFAULT). The register also provides information about the actual Boot Flash selection (status bit CURRENT_BOOT_SELECT) and the IPMC selected Boot Flash (status bit TARGET_BOOT_SELECT). ATCA-7480 Installation and Use (6806800T17A)

  • Page 158: Table 5-77 Flash Status Register

    1: Selects Recover Boot SPI Flash. TARGET_BOOT_SELECT. Target Boot Flash Selection. PWR_GOOD: LPC: r 0: Selects Default Boot SPI Flash IPMC: r/w 1: Selects Recovery Boot SPI Flash Note: New flash selection valid with next platform reset ATCA-7480 Installation and Use (6806800T17A)

  • Page 159: Pch Output Enable Register

    SPI master protocol. The signal, RTM_SPI_MISO is also used to signal an ARTM interrupt to the base board. See Chapter 5.18.4 RTM Interrupt Status Register. At the moment there is no ARTM with an SPI interface defined. ATCA-7480 Installation and Use (6806800T17A)

  • Page 160: Table 5-79 Rtm Spi Address/Command Register

    A write access to the RTM SPI Address/Command Register with the Command Bit 1 (Read) starts a SPI read transaction. This contains the data read from the SPI device. Table 5-81 RTM SPI Read Register Address Offset: 0x43 Description Default Access RTM SPI read data LPC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 161: Update Channel Equalization Control Register

    1: UC3_EQ_TX is tri-state. Control output Signal UC4_EQ_RX: LPC: r/w 0: UC4_EQ_RX is driven low. IPMC: r 1: UC4_EQ_RX is tri-state. Control output Signal UC4_EQ_TX: LPC: r/w 0: UC4_EQ_TX is driven low. IPMC: r 1: UC4_EQ_TX is tri-state. ATCA-7480 Installation and Use (6806800T17A)

  • Page 162: Rtm Usb Control Register

    Faceplate Ethernet 1 Interrupt (signal PV_FPETH_1_INT_): IPCM: r/w1c 0: No interrupt 1: Interrupt detected. (falling edge PV_FPETH_1_INT_) Base Ethernet 1 Interrupt (signal PV_BASE_1_INT_): IPCM: r/w1c 0: No interrupt 1: Interrupt detected. (falling edge PV_BASE_1_INT_) Reserved IPMC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 163: Led Status And Control Register

    Table 5-87 Spare Signal Status Register Address Offset: 0x52 Description Default Access Signal level of SW100_2 (Connected to SW100.2) Ext. Signal level of SW1.4 (Connected to SW1.4) Ext. Signal level of spare connections SPARE[2:1] Ext. Reserved Ext. ATCA-7480 Installation and Use (6806800T17A)

  • Page 164: Cpu Presence Detection Register

    Bit 0 = Non critical Error CPU_ERR_[1] Ext. Bit 1 = Non-fatal error (operating system or CPU_ERR_[2] Ext. firmware action required to contain and recover) Bit 2 = Fatal error (system reset likely required to recover) Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 165: Telecom Clock Supervision Registers

    SYSCLK_IN_CLK2A CLK2A from backplane SYSCLK_IN_CLK2B CLK2B from backplane Table 5-91 Telecom Clock Monitor Control Register Address: 0x60 Description Default Access Enable supervised LPC: r/w Telecom Clock 0 to 3 Set corresponding bit enable monitoring. Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 166: Table 5-92 Telecom Clock Monitor Status Register

    > Upper limit Period Mode: Corresponding bit is set when the Clock 0 Period within the selected time base is: < Lower limit or > Upper limit Clearing bit triggers new sequence of measurements. Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 167: Table 5-94 Telecom Clock Monitor Select Register

    Address: 0x63 Description Default Access Select supervised Telecom Clocks. See Table 5-90 Supervised LPC: r/w Telecom Clocks Reference List: 0-3: Select corresponding clock. Reserved The following tables refer to the clock selected with Table 5-94. ATCA-7480 Installation and Use (6806800T17A)

  • Page 168: Table 5-95 Telecom Clock Monitor Time Base Register

    6: Period Counter incremented with each 64th master clock 7: Period Counter incremented with each 128th master clock 8: Period Counter incremented with each 256th master clock 9 and all others: Period Counter incremented with each 512th master clock Reserved ATCA-7480 Installation and Use (6806800T17A)

  • Page 169: Table 5-96 Telecom Clock Monitor Frequency/Period Register

    Clock Monitor Status Register is set. Table 5-97 Telecom Clock Monitor Lower Limit Register Address: 0x67 -0x68 Description Default Access 15:0 Lower Limit for supervised Telecom Clock: LPC: r/w Used by Table 5-93 Telecom Clock Monitor Out of Range Register. ATCA-7480 Installation and Use (6806800T17A)

  • Page 170: Bios Version Registers

    Description Default Access BIOS Version bits 8 to 15 LPC: r/w IPMC: r Table 5-101 BIOS Version Register 3 Address Offset: 0x76 Description Default Access BIOS Version bits 16 to 23 LPC: r/w IPMC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 171: Ipmc Bios Communication Registers

    Address Offset: 0x7C Description Default Access IPMC BIOS Communication bits PWR_GOOD:0 LPC: r/w IPMC: r/w 5.1.30 Scratch Registers Table 5-105 LPC Scratch Register Address Offset: 0x7D Description Default Access LPC Scratch bits. PWR_GOOD:0 LPC: r/w IPMC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 172: Table 5-106 Ipmc Scratch Register

    Maps and Registers Table 5-106 IPMC Scratch Register Address Offset: 0x7E Description Default Access LPC Scratch bits. PWR_GOOD:0 IPMC: r/w LPC: r ATCA-7480 Installation and Use (6806800T17A)

  • Page 173: Bios

    System Boot Options Parameter #96 on page 234. The BIOS used on the blade is based on the Insyde UEFI BIOS with several Artesyn Embedded Technologies extensions integrated. Its main features are: Initialize CPU, chipset and memory ...

  • Page 174: Accessing The Blade Using The Serial Console Redirection

    Terminal emulation programs such as TeraTermPro or Putty can be used. 6.2.2 Default Access Parameters By default, the blade can be accessed using the serial interface COM1. By default, this interface is accessible using a RJ-45 connector at the blade's faceplate. ATCA-7480 Installation and Use (6806800T17A)

  • Page 175: Connecting To The Blade

    3. Connect NULL-modem cable to COM port of the blade. 4. Start up the blade. Changing Configuration Settings When the system is switched on or rebooted, the presence and functionality of the system components is tested by Power-On Self-Test (POST). ATCA-7480 Installation and Use (6806800T17A)
  • Page 176 In order to navigate in setup, use the arrow keys on the keyboard to highlight items on the menu. All other navigation possibilities are shown at the bottom of the menu. Additionally, an item-specific help is displayed on the right side of the window. ATCA-7480 Installation and Use (6806800T17A)

  • Page 177: Boot Options

    There are two possibilities to determine the device from which BIOS attempts to boot: By setup, to select a permanent order of boot devices  By boot selection menu, to select any device for the next boot-up procedure only  ATCA-7480 Installation and Use (6806800T17A)
  • Page 178 If BIOS is not successful at booting from one device, it tries to boot from the next device on the list. When BIOS does not find any bootable device, the board will be restarted by a cold reset. ATCA-7480 Installation and Use (6806800T17A)

  • Page 179: By Boot Menu

    1. Press F4 key to enter the Boot Menu. Figure 6-2 Boot Menu 2. Override existing boot sequence by selecting another boot device from the boot list. If the selected device does not load the operating system, BIOS will reset the blade. ATCA-7480 Installation and Use (6806800T17A)

  • Page 180: Ipmi Boot Parameter

    BIOS setup parameter and an IPMI boot parameter interact. Figure 6-3 IPMI Boot Parameter BIOS Flash 1 BIOS Flash 2 BIOS Parameter Boot Parameter Storage (EEPROM) Default Parameter BIOS USER Read/Write Private I2C DEFUALT IPMC Read Only IPMB-0 To ShMM ATCA-7480 Installation and Use (6806800T17A)

  • Page 181: Bios Setup Configuration

    5. BIOS writes the parameter to the BIOS Parameter in the Flash. 6. BIOS writes the parameter to the IPMI Boot Parameter USER area. BIOS Setup Configuration This section provides information about the various configurations at BIOS setup. ATCA-7480 Installation and Use (6806800T17A)

  • Page 182: Main

    IPMI Boot parameter Description System Time [15:48:21] Set the Time. Use Enter to switch between Time elements. System Date [Thu 11/11/2014] Set the Date. Use Enter to switch between Date elements. 6.6.2 Advanced Platform Information ATCA-7480 Installation and Use (6806800T17A)

  • Page 183: Figure 6-5 Platform Information

    BIOS This shows important information about Platform, CPU, QPI and Memory. Figure 6-5 Platform Information ATCA-7480 Installation and Use (6806800T17A)

  • Page 184: Table 6-2 Advanced >> Rtm Configuration

    Express parameter are set for this RTM. If Disabled disabled, the RTM PCI Express parameter can be set manually. CPU0 PCIe to RTM X4x4x4x4 rtm_cpu0_bif Selects CPU0 PCIe Bifurcation for Zone 3 Width connector (RTM). x4x4x8 x8x4x4 x8x8 ATCA-7480 Installation and Use (6806800T17A)

  • Page 185: Table

    Gen 2 (5 GT/s) Gen 3 (8 GT/s) CPU1 PCIe Port 3B Auto rtm_cpu1_3b Selects CPU1 PCIe Port 3B Speed for Zone 3 connector (RTM). Gen 1 (2.5 GT/s) Gen 2 (5 GT/s) Gen 3 (8 GT/s) ATCA-7480 Installation and Use (6806800T17A)

  • Page 186: Figure 6-7 Peripheral Configuration

    CPU1 PCIe Port 3D Auto rtm_cpu1_3d Selects CPU1 PCIe Port 3D Speed for Zone 3 connector (RTM). Gen 1 (2.5 GT/s) Gen 2 (5 GT/s) Gen 3 (8 GT/s) Peripheral Configuration Figure 6-7 Peripheral Configuration ATCA-7480 Installation and Use (6806800T17A)

  • Page 187: Table 6-3 Advanced >> Peripheral Configuration

    Pci 64-bit Decode Enabled, Disabled pci_64bit Allows system to support 64-bit BAR for PCI devices. Spread Spectrum Enabled, Disabled clock_ssc Enables/Disables Spread Spectrum Clock setting to affect EMI Front Panel Ethernet. Figure 6-8 Peripheral Intel VT Configuration ATCA-7480 Installation and Use (6806800T17A)

  • Page 188: Table 6-4 Advanced >> Peripheral Configuration >> Intel Vt For Directed I/O (Vt-D)

    Enables/Disables Intel Virtualization (VT-d) Technology for Directed I/O (VT-d) by reporting the I/O device assignment to VMM through DMAR ACPI Tables. Interrupt Remapping Enabled, Disabled vtd_ir Enables/Disables VT_D Interrupt Remapping Support. SATA Configuration Figure 6-9 SATA Configuration ATCA-7480 Installation and Use (6806800T17A)

  • Page 189: Table 6-5 Advanced >> Sata Configuration

    Management (SALP). SATA Speed Support 1.5 Gb/s, 3.0 sata_speed Indicates the maximum speed the SATA Gb/s, 6.0 Gb/s controller can support on its ports (Only usable in AHCI/RAID mode). USB Configuration Figure 6-10 USB Configuration ATCA-7480 Installation and Use (6806800T17A)

  • Page 190: Table 6-6 Advanced >> Usb Configuration

    Enabled, usb_rtm Enables/Disables USB to RTM. Disabled USB1 3.0 Front Panel Enabled, usb1_3 Enables/Disables USB1 Front Panel USB 3.0 Disabled support. USB2 3.0 Front Panel Enabled, usb2_3 Enables/Disables USB2 Front Panel USB 3.0 Disabled support. ATCA-7480 Installation and Use (6806800T17A)

  • Page 191: Table 6-7 Advanced >> Processor Configuration

    Valid Range: 0 to 3FFE. 3FFF=Disabling all cores: Invalid Socket 1 Core 0 to 3FFE cpu1_dism Core Disable Bitmap Hex Value. Disable 0: Enable all cores. Valid Range: 0 to 3FFE. 3FFF=Disabling all cores: Invalid ATCA-7480 Installation and Use (6806800T17A)

  • Page 192: Table

    When disabled, optimizes the system for applications that require high utilization of random memory access. Direct Cache Enabled, cpu_dca Enables/Disables Direct Cache Access (DCA). Access Disabled X2APIC Enabled, cpu_x2apic Enables/Disables extended APIC support. Disabled ATCA-7480 Installation and Use (6806800T17A)

  • Page 193: Table 6-8 Advanced >> Processor Configuration >> Processor Power Management Configuration

    When Power Optimized is selected, Intel Turbo Power Boost Technology engages after performance Optimized state P0 is sustained for more than 2 seconds. When Traditional is selected, Intel Turbo Boost Technology is engaged even for P0 requests less than 2 seconds. ATCA-7480 Installation and Use (6806800T17A)

  • Page 194: Table

    Enhanced Halt State Enabled, Cpu_c1e Enables the Enhanced C1E state of the CPU (C1E) Disabled Report ACPI Cx State ACPI C2, ACPI cpu_cxacpi Report CPU C3/C6 state to OS as ACPI C2 or ACPI C3 state. ATCA-7480 Installation and Use (6806800T17A)

  • Page 195: Table 6-9 Advanced >> Memory Configuration

    MHz. Halt on Training Enabled, Disabled mem_halt Enables/Disables Halt on Memory Training Error Error. NUMA Enabled, Disabled mem_numa Enables/Disables Non Uniform Memory Access (NUMA). Hardware Memory Disabled, Short, mem_test Select Hardware Memory Test Test Long ATCA-7480 Installation and Use (6806800T17A)

  • Page 196: Table 6-10 Advanced >> Memory Configuration >> Memory Ras Configuration

    Mirroring is not supported. Incase if enabled, Sparing will be selected. Memory Enabled, mem_sparing Enables/Disables Memory Rank Sparing. Rank Sparing Disabled Patrol Scrub Enabled, mem_ps Enables/Disables Patrol Scrub. Disabled Demand Enabled, mem_ds Enables/Disables Demand Scrub. Scrub Disabled ATCA-7480 Installation and Use (6806800T17A)

  • Page 197: Table 6-11 Advanced >> Console Redirection

    115200, 57600, con_br Sets Console Redirection baud rate. 38400, 19200, 9600, 4800, 2400, 1200 Data Bits 7 Bits, 8 Bits con_db Sets Console Redirection data bits. Parity None, Even, Odd con_par Sets Console Redirection parity bits. ATCA-7480 Installation and Use (6806800T17A)

  • Page 198: Figure 6-16 Apei Configuration

    Sets Console Redirection stop bits. Flow Control None, RTS/CTS, con_fc Sets Console Redirection flow control type. XON/XOFF C.R. After Yes, No con_ap Continue Console Redirection after POST, when Post OS is loaded. APEI Configuration Figure 6-16 APEI Configuration ATCA-7480 Installation and Use (6806800T17A)

  • Page 199: Table 6-12 Advanced >> Apei Configuration

    ALL, BIOS, BMC Settings Events to log Selected Storage. SEL, MEMORY Advanced >> BIOS Event Log Configuration >> Event Log Viewer The Event Log Viewer is used to view the event logs of all storages. ATCA-7480 Installation and Use (6806800T17A)

  • Page 200: Table 6-14 Advanced >> Ipmi Configuration

    The OS has to shut off the watchdog timer when successfully booted. 0S WD Timeout 1, 2, 3, 5, 7, osboot_wd_tout Configure the Timeout of the OS Boot Watchdog 10, 15, 20 Timer. Minutes ATCA-7480 Installation and Use (6806800T17A)
  • Page 201 No Change: Fail Safe Policy will not be changed by BIOS. Show Sensor Data Shows Sensor Data Records (SDR). Lists all SDR information provided by the IPMC. Execute IPMI Executes IPMI Utility for debugging purpose only. Debut Utility ATCA-7480 Installation and Use (6806800T17A)

  • Page 202: Security

    Enables/Disables TPM Function. This option will Disable and automatically return to No-Operation. Deactivate, Enable and Activate Set Supervisor Install or Change the password and the length of Password password must be greater than one character. ATCA-7480 Installation and Use (6806800T17A)

  • Page 203: Boot

    Select boot type to Dual type, Legacy type or UEFI Legacy Boot type. Dual boot type supports boot from Legacy Type, UEFI boot and UEFI. Type Boot Priority EFI First, Legacy boot_priority Determine whether EFI devices or Legacy devices First are booted first. ATCA-7480 Installation and Use (6806800T17A)

  • Page 204: Table

    SAS controller. Select Enabled when RTM SAS Boot is required. USB Boot Enabled, boot_usb Disables/Enables booting from USB port devices. Disabled Info Screen 0 .. 10 info_tmout The number of seconds that the firmware will wait Timeout for <F2> key. ATCA-7480 Installation and Use (6806800T17A)

  • Page 205: Figure 6-20 Efi Boot Order

    Use '+' and '-' keys to move the devices up or down. With the '!' key, a boot device can be enabled or disabled. If the boot entry shows '!' as first character, this boot entry is disabled. ATCA-7480 Installation and Use (6806800T17A)

  • Page 206: Figure 6-21 Legacy Boot Order

    Use '+' and '-' keys to move the devices up or down. With the '!' key, a boot device can be enabled or disabled. If the boot entry shows '!' as first character, this boot entry is disabled. ATCA-7480 Installation and Use (6806800T17A)

  • Page 207: Exit

    Saves the changes made and then exits the system. Save Change Without Exit Saves the changes without exiting the system. Exit Discarding Changes Exits the system without saving the changes. Load Defaults Loads default Settings. Discard Changes Discards the changes. ATCA-7480 Installation and Use (6806800T17A)

  • Page 208: Uefi Secure Boot

    3. Install and power up the blade. 4. Wait until the blade has completely booted and is up and running. 5. Remove the blade from the system again. 6. Set switch SW3-4 to OFF. Now the BIOS default settings are restored. ATCA-7480 Installation and Use (6806800T17A)

  • Page 209: Ipmi Support

    BIOS IPMI Support The ATCA-7480 BIOS provides the following IPMI support: Sets initial timestamp for IPMI SEL events.  Sends Boot Initiated event  Sends Memory DIMM detect and error events  Sends system firmware progress events  Reads IPMC version of the main board and the RTM ...

  • Page 210: Bios Error Logging

    - Correctable ECC Memory Error Correctable: Correctable memory log disabled Sensor: Memory, Offset 05h - Memory Error Limit Reached - Correctable ECC logging limit reached Uncorrectable: Multi-bit ECC memory error Sensor: Memory, Offset 01h - Uncorrectable ECC Memory Error ATCA-7480 Installation and Use (6806800T17A)
  • Page 211 BIOS Table 6-18 Logged Error Events (continued) Error SMIBIOS IPMI PCI PERR PCI Parity Error Sensor: Critical Interrupt, Offset 04h PCI PERR PCI SERR PCI System Error Sensor: Critical Interrupt, Offset 05h PCI SERR ATCA-7480 Installation and Use (6806800T17A)

  • Page 212: Ipmi Error Logging

    71h Base Network not detected 72h Fabric Network not detected 73h Accelerator Device not detected 74h RTM SAS Controller not detected 75h RTM Network not detected 76h RTM PCI Bridge not detected 80h Front Panel Network reduced PCI performance ATCA-7480 Installation and Use (6806800T17A)
  • Page 213 A1h RTM-ATCA-747X-10G-SP detected A2h RTM-ATCA-747X-10G-D detected A3h RTM-ATCA-736X-10G-SP detected A4h RTM-ATCA-736X-10G-SAS detected A5h RTM-ATCA-748X-40G detected A6h RTM-ATCA-7360 detected A7h RTM-ATCA-736X-DD detected A8h RTM-ATCA-736X-10G-SP detected AAh RTM-ATCA-736X-10G-SAS detected ABh RTM-ATCA-748X-40G-HA detected ACh SB-RTM451 detected ADh RTM-URA50 detected ATCA-7480 Installation and Use (6806800T17A)

  • Page 214: Led Usage

    "POST code" sensor is only valid when the board is in the BIOS phase. The reading can be used to locate the cause of a board hang during BIOS phase. When the board has booted a OS, the reading of the '"POST code" sensor returns no valid status code. ATCA-7480 Installation and Use (6806800T17A)

  • Page 215: Table 6-20 Bios Post Codes

    South Bridge Early Initial PCIE Training TPM Initial SMBUS Early Initial Clock Generator Initial Internal Graphic device early initial, PEI_IGDOpRegion HECI Initial Watchdog timer initial Memory Initial for Normal boot Memory Initial for Crisis Recovery ATCA-7480 Installation and Use (6806800T17A)
  • Page 216 Setup SMM ACCESS service North bridge Middle initial Super I/O DXE initial Setup Legacy Region service, DXE_LegacyRegion South Bridge Middle Initial Identify Flash device Fault Tolerant Write verification Variable Service Initial Fail to initial Variable Service ATCA-7480 Installation and Use (6806800T17A)
  • Page 217 PPM Initial HECIDRV Initial Variable store garbage collection and reclaim operation Do not support flash part (which is defined in SpiDevice.c) Enter BDS entry Install Hotkey service ASF Initial PCI enumeration PCI resource assign complete ATCA-7480 Installation and Use (6806800T17A)
  • Page 218 Enter Setup Menu Enter Boot manager Try to boot system to OS Shadow Misc Option ROM Save S3 resume required data in RAM Last Chipset initial before boot to OS Start to boot Legacy OS ATCA-7480 Installation and Use (6806800T17A)
  • Page 219 OS call ACPI disable function ACPI disable function complete Memory initial for S3 resume Get S3 resume required data from memory Start to use memory during S3 resume Set cache for physical memory during S3 resume ATCA-7480 Installation and Use (6806800T17A)

  • Page 220: Table

    QPI Initialization: Setup IO SADs in PBSP to access the config space QPI Initialization: System configurations that require some kind of reset QPI Initialization: Sync up with PBSPs QPI Initialization: Topology discovery and route calculation QPI Initialization: Program final route ATCA-7480 Installation and Use (6806800T17A)
  • Page 221 Memory Initialization: JEDEC Init Memory Initialization: Channel Training Memory Initialization: Throttling Init Memory Initialization: BIST Memory Initialization: Init Memory Initialization: DDR Memory Mapping Memory Initialization: RAS Configuration Memory Initialization: Get Margins Memory Initialization: MRC Done ATCA-7480 Installation and Use (6806800T17A)
  • Page 222 BIOS ATCA-7480 Installation and Use (6806800T17A)

  • Page 223: Serial Over Lan

    Installing the ipmitool You can download the open source tool ipmitool from http://ipmitool.sourceforge.net (at the time of publishing this manual the current version is 1.8.13). Documentation for this tool is also freely available on this site. ATCA-7480 Installation and Use (6806800T17A)

  • Page 224: Configuring Sol Parameters

    You can use standard IPMI commands or the ipmitool to modify the parameters. 7.3.1 Using Standard IPMI Commands This example shows how to setup the SOL configuration parameter with standard IPMI commands. ipmicmd is used on the local IPMC and the IP is configured. ATCA-7480 Installation and Use (6806800T17A)

  • Page 225: Using Ipmitool

    SOL session for base 0 (channel 1) and base 1 (channel 2): root@localhost:~# ipmitool lan print 1 Set in Progress : Set Complete Auth Type Support Auth Type Enable : Callback : : User : Operator : : Admin ATCA-7480 Installation and Use (6806800T17A)
  • Page 226 : User : Operator : : Admin : OEM IP Address Source : Unspecified IP Address : 172.17.1.220 Subnet Mask : 255.255.0.0 MAC Address : ec:9e:cd:10:a0:65 Default Gateway IP : 172.17.0.1 Default Gateway MAC : 00:00:00:00:00:00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 227: Establishing An Sol Session

    2. Compile and install the ipmitool on your target, which is destined for opening the SOL session on the ATCA-7480. For details refer to Installing the ipmitool on page 223. 3. Apply an IP address to the ATCA-7480 SOL interface. For details, see to Configuring SOL Parameters on page 224.
  • Page 228 To see the BIOS serial interface in SOL Session operational. Use ~? For help it might be necessary to write a logical "1" into FPGA register offset 0x04 (ipmicmd -k "f 0 6 52 1 fe 0 4 1" smi 0) - This is needed with BIOS version prototypes. ATCA-7480 Installation and Use (6806800T17A)

  • Page 229: Supported Ipmi Commands

    Set BMC Global Enables 0x06/0x07 0x2E Get BMC Global Enables 0x06/0x07 0x2F Clear Message Flags 0x06/0x07 0x30 Get Message Flags 0x06/0x07 0x31 Get Message 0x06/0x07 0x33 Send Message 0x06/0x07 0x34 Set Channel Access 0x06/0x07 0x40 ATCA-7480 Installation and Use (6806800T17A)

  • Page 230: Watchdog Commands

    2 sensor. The pre-timeout and power-cycle options are not supported. Table 8-3 Supported Watchdog Commands Command NetFn (Request/Response) Reset Watchdog Timer 0x06/0x07 0x22 Set Watchdog Timer 0x06/0x07 0x24 Get Watchdog Timer 0x06/0x07 0x25 ATCA-7480 Installation and Use (6806800T17A)

  • Page 231: Sel Device Commands

    Set SEL Time 0x0A/0x0B 0x49 8.1.5 FRU Inventory Commands Table 8-5 Supported FRU Inventory Commands Command NetFn (Request/Response) Get FRU Inventory Area Info 0x0A/0x0B 0x10 Read FRU Data 0x0A/0x0B 0x11 Write FRU Data 0x0A/0x0B 0x12 ATCA-7480 Installation and Use (6806800T17A)

  • Page 232: Sensor Device Commands

    Get Sensor Event Enable 0x04/0x05 0x29 Get Sensor Event Status 0x04/0x05 0x2B Get Sensor Reading 0x04/0x05 0x2D Get Sensor Type 0x04/0x05 0x2F Set Event Receiver 0x04/0x05 0x00 Get Event Receiver 0x04/0x05 0x01 Platform Event 0x04/0x05 0x02 ATCA-7480 Installation and Use (6806800T17A)

  • Page 233: Chassis Device Commands

    Configurable Boot Property Corresponding Boot Parameter Number Selection between default and backup boot flash as device to boot from Selection between default and backup EEPROM as device where the on-board FPGA loads its configuration stream from ATCA-7480 Installation and Use (6806800T17A)

  • Page 234: Table 8-9 System Boot Options Parameter #96

    Corresponding Boot Parameter Number Timeout for graceful shutdown BIOS boot parameters. 8.1.7.1.1 System Boot Options Parameter #96 This boot parameter is an Artesyn-specific OEM boot parameter. Its definition is given in the following table. Table 8-9 System Boot Options Parameter #96 Data Byte...

  • Page 235: Table 8-10 System Boot Options Parameter #98

    IPMI user and default is, the area which the boot firmware reads out and uses during the boot process. The default area can only be read by both the IPMI user and the boot firmware. Its purpose is to store factory-programmed default boot options which can ATCA-7480 Installation and Use (6806800T17A)

  • Page 236: Table 8-11 System Boot Options - Parameter #100 - Data Format

    When reading from the storage area and you find any of these two values, your software should assume that no user-specific boot options have previously been written to the storage area. ATCA-7480 Installation and Use (6806800T17A)

  • Page 237: Table 8-12 System Boot Options Parameter #100 - Set Command Usage

    Bits 6..0: must contain the value: "100", indicating this OEM system boot option. Set Selector Must be set to "0" (user area). You can only write to the user area, therefore no other values are supported. ATCA-7480 Installation and Use (6806800T17A)

  • Page 238: Table 8-13 System Boot Options Parameter #100 - Get Command Usage

    Zero based index of the 16-byte block which you want to read from. Index 0 refers to the first block of 16 bytes, which includes the first two bytes which indicate the boot parameter data size. Response Data ATCA-7480 Installation and Use (6806800T17A)

  • Page 239: Table 8-14 System Boot Options Parameter #100 - Supported Parameters

    This is supported by HPI, for details refer to the System Management Interface Based on HPI-B User’s Guide related to your system environment. Artesyn Embedded Technologies provides the tool "ipmibpar" to interpret the ASCII parameters. To obtain the tool, contact your local sales representative.
  • Page 240 Selects CPU1 PCIe Port 3A Speed for Zone auto 3 connector (RTM). gen1 gen2 gen3 rtm_cpu1_3b Selects CPU1 PCIe Port 3B Speed for Zone auto 3 connector (RTM). gen1 gen2 gen3 ATCA-7480 Installation and Use (6806800T17A)

  • Page 241: Table

    64-bit BAR support for PCI devices clock_ssc Spread Spectrum Clock Intel Virtualization Technology for Directed I/O (VT-d) vtd_ir VT-d Interrupt Remapping Support. Sata SATA controller Operation Mode ahci raid sata_alpm Aggressive Link Power Management (SALP) sata_speed maximum SATA speed ATCA-7480 Installation and Use (6806800T17A)
  • Page 242 Valid Range: 0 to 3FFE. 0 to 3FFE 3FFF=Disabling all cores: Invalid cpu_ht CPU Hyper Threading cpu_ed CPU Execute Disable cpu_txt Intel Trusted Execution Technology (TXT). cpu_vt CPU Virtualization (VT-x) cpu_hp CPU Hardware Prefetcher cpu_acp CPU Adjacent Cache Prefetcher ATCA-7480 Installation and Use (6806800T17A)

  • Page 243: Table

    Package C State limit c0c1 c6nr cpu_c3 CPU C3 report cpu_c6 CPU C6 report cpu_c1e CPU Enhanced Halt State (C1E) cpu_cxacpi Report ACPI Cx State mem_speed Memory Frequency (MHz) auto 1333 1600 1867 2133 ATCA-7480 Installation and Use (6806800T17A)
  • Page 244 Memory Patrol Scrub mem_ds Memory Demand Scrub con_tt Serial console terminal type vt100 vt100+ utf8 ansi con_br Serial console baud rate 9600 19200 38400 57600 115200 con_db Serial console data bits con_par Serial console parity bits ATCA-7480 Installation and Use (6806800T17A)
  • Page 245 UEFI revision of APEI error format uefi22 uefi23 ipmi_irq IPMI KCS Interrupt osboot_wd OS Watchdog Timer osboot_wd_tout 0S Watchdog Timeout in minutes osboot_wd_action 0S Watchdog Timeout Action noaction reset poweroff powercycle failsafe IPMI Fail Safe nochange ATCA-7480 Installation and Use (6806800T17A)
  • Page 246 RTM SAS disk Boot boot_usb USB device boot info_tmout The number of seconds that the firmware will wait for <F2> key boot_oder Set the Boot Order device1… deviceN separated by comma See next table ATCA-7480 Installation and Use (6806800T17A)

  • Page 247: Table 8-15 Boot_Order Devices

    RTM Network 4 rtmnet5 RTM Network 5 rtmnet6 RTM Network 6 rtmnet7 RTM Network 7 rtmnet8 RTM Network 8 rtmnet9 RTM Network 9 rtmnet10 RTM Network 10 usbcdrom USB CDROM/DVDROM usbcdrom1 USB CDROM/DVDROM connected to USB1 ATCA-7480 Installation and Use (6806800T17A)
  • Page 248 EFI RTM Network 7 (IPv4) efirtmnet8 EFI RTM Network 8 (IPv4) efirtmnet9 EFI RTM Network 9 (IPv4) efirtmnet10 EFI RTM Network 10 (IPv4) eiffrontnet1v6 EFI Front Panel Network 1 (IPv6) efifrontnet2v6 EFI Front Panel Network 2 (IPv6) ATCA-7480 Installation and Use (6806800T17A)
  • Page 249 EFI Boot from USB device connected to USB2 eifusb3 EFI Boot from USB device connected to USB RTM windows Windows Boot Manager redhat RedHat Linux suse SuSE Linux ubuntu Ubuntu Linux fedora Fedora Linux ATCA-7480 Installation and Use (6806800T17A)

  • Page 250: Lan Device Commands

    0x0C/0x0D 0x22 PICMG 3.0 Commands The Artesyn Embedded Technologies IPMC is a fully compliant AdvancedTCA intelligent Platform Management Controller. It supports all required and mandatory AdvancedTCA commands as defined in the PICMG 3.0 and AMC.0 R2.0 specifications. Table 8-17 Supported PICMG 3.0 Commands...
  • Page 251 0x31 Upload firmware block 0x2C/0x2D 0x32 Finish firmware upload 0x2C/0x2D 0x33 Get upgrade status 0x2C/0x2D 0x34 Activate firmware 0x2C/0x2D 0x35 Query self-test results 0x2C/0x2D 0x36 Query rollback status 0x2C/0x2D 0x37 Initiate manual rollback 0x2C/0x2D 0x38 ATCA-7480 Installation and Use (6806800T17A)

  • Page 252: Artesyn Embedded Technologies Specific Commands

    Commands The Artesyn Embedded Technologies IPMC supports several commands which are not defined in the IPMI or PICMG 3.0 specification but are introduced by Artesyn Embedded Technologies: serial output commands. Before sending any of these commands, the shelf management software must check ...

  • Page 253: Set Serial Output Command

    Table 8-19 Request Data of Set Serial Output Command Byte Data Field LSB of Artesyn IANA Enterprise number. A value of 0xCD has to be used. Second byte of Artesyn Embedded Technologies IANA Enterprise number. A value of 0x65 has to be used.

  • Page 254: Get Serial Output Command

    Table 8-21 Request Data of Get Serial Output Command Byte Data Field LSB of Artesyn Embedded Technologies IANA Enterprise number. A value of 0xCD has to be used. Second byte of Artesyn Embedded Technologies IANA Enterprise number. A value of 0x65 has to be used.

  • Page 255: Oem Command To Configure Ipmi Features

    Byte Data Field Completion code LSB of Artesyn Embedded Technologies IANA Enterprise number. Second byte of Artesyn Embedded Technologies IANA Enterprise number. MSB of Artesyn Embedded Technologies IANA Enterprise number. Serial output selector 8.3.2 OEM Command to configure IPMI Features...

  • Page 256: Set Feature Configuration

    Table 8-24 Set Feature Configuration Command Byte Data Field Request Data LSB of Artesyn IANA Enterprise Number. A value of CDh shall be used. 2nd byte of Artesyn IANA Enterprise Number. A value of 65h shall be used. MSB of Artesyn IANA Enterprise Number. A value of 00h shall be used.

  • Page 257: Get Feature Configuration

    Table 8-26 Get Feature Configuration Command Byte Data Field Request Data LSB of Artesyn IANA Enterprise Number. A value of CDh shall be used. 2nd byte of Artesyn IANA Enterprise Number. A value of 65h shall be used. MSB of Artesyn IANA Enterprise Number. A value of 00h shall be used.

  • Page 258: Pigeon Point Specific Commands

    Completion Code. Generic plus the following command- specific completion codes: 80h = feature selector not supported. LSB of Artesyn IANA Enterprise Number. A value of CDh shall be used. 2nd byte of Artesyn IANA Enterprise Number. A value of 65h shall be used.
  • Page 259 Table 8-47 on page 275 0x2E/0x2F 0x27 Enable Module Site Table 8-48 on page 277 0x2E/0x2F 0x28 Disable Module Site Table 8-49 on page 277 0x2E/0x2F 0x29 Reset Carrier SDR repository Table 8-50 on page 278 0x2E/0x2F 0x33 ATCA-7480 Installation and Use (6806800T17A)

  • Page 260: Get Status Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)
  • Page 261 Bits [0:3] Metallic Bus 1 Events These bits indicate pending Metallic Bus 1 requests arrived from the shelf manager: 0: Metallic Bus 1 Query 1: Metallic Bus 1 Release 2: Metallic Bus 1 Force 3: Metallic Bus 1 Free ATCA-7480 Installation and Use (6806800T17A)
  • Page 262 Bits [0:3] Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the shelf manager 0: Clock Bus 3 Query 1: Clock Bus 3 Release 2: Clock Bus 3 Force 3: Clock Bus 3 Free ATCA-7480 Installation and Use (6806800T17A)

  • Page 263: Get Serial Interface Properties Command

    Bits [6:4] Reserved Bits [3:0] Baud Rate ID The baud rate ID defines the interface baud rate as follows: 0: 9600 bps 1: 19200 bps 2: 38400 bps 3: 57600 bps (unsupported) 4: 115200 bps (unsupported) ATCA-7480 Installation and Use (6806800T17A)

  • Page 264: Set Serial Interface Properties Command

    3: 57600 bps (unsupported) 4: 115200 bps (unsupported) Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 265: Get Debug Level Command

    Bit [1] Low-level Error Logging Enable If set to "1", the IPMC outputs low-level error/diagnostic messages onto the serial debug interface. Bit [0] Error Logging Enable If set to "1", the IPMC outputs error/diagnostic messages onto the serial debug interface. ATCA-7480 Installation and Use (6806800T17A)

  • Page 266: Set Debug Level Command

    Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 267: Get Hardware Address Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Hardware Address If set to 00, the ability to override the hardware address is disabled. Note: A hardware address change only takes effect after an IPMC reset. Response Data Completion Code ATCA-7480 Installation and Use (6806800T17A)

  • Page 268: Get Handle Switch Command

    LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 Handle Switch Status 0x00: The handle switch is open. 0x01: The handle switch is closed. 0x02: The handle switch state is read from hardware. ATCA-7480 Installation and Use (6806800T17A)

  • Page 269: Set Handle Switch Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 270: Set Payload Communication Time-Out Command

    0.1 to 25.5 seconds. Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 271: Enable Payload Control Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 272: Reset Ipmc Command

    Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code ATCA-7480 Installation and Use (6806800T17A)

  • Page 273: Graceful Reset Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 274: Get Payload Shutdown Time-Out Command

    Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 Time-Out measured in hundreds of milliseconds, LSB first ATCA-7480 Installation and Use (6806800T17A)

  • Page 275: Set Payload Shutdown Time-Out Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Module Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)
  • Page 276 0: Payload power is bad. 1: Payload power is good. Bit [6] 0: IPMB-L buffer is not attached. 1: IPMB-L buffer is attached. Bit [7] 0: IPMB-L buffer is not ready. 1: IPMB-L buffer is ready. ATCA-7480 Installation and Use (6806800T17A)

  • Page 277: Enable Module Site Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Module Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 278: Reset Carrier Sdr Repository Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7480 Installation and Use (6806800T17A)

  • Page 279: Ipmi Feature Set

    Chapter 9 IPMI Feature Set The ATCA-7480 provides an intelligent hardware management system, as defined in the AdvancedTCA® Base Specification (PICMG® 3.0; AMC.0). This system incorporates two IPMI controllers: An Intelligent Platform Management Controller (IPMC) based on the BMR-A2F-AMCc® ...
  • Page 280 Registers within the Glue Logic FPGA can be accessed by the IPMC via I2C bus. This enhances the capabilities of the IPMC. The Glue Logic FPGA is used to monitor the CPU status, the payload reset cause, the power failure registers, and to control the BIOS boot bank selection. ATCA-7480 Installation and Use (6806800T17A)

  • Page 281: Figure 9-1 Ipmc Block Diagram Of Atca-7480

    IPMI Feature Set A functional block diagram of the ATCA-7480 IPMC/MMC system is shown below. Figure 9-1 IPMC block diagram of ATCA-7480 front Intel CPU Lattice GLUE (FPGA) 0xFD, 0xFE LM75 TEMP FRU EEPROM 0xA2 SEL EEPROM LM75 inlet 0xA0...

  • Page 282: Firmware Architecture

    The IPMC provides a number of subsidiary threads to serve RTM module discovery and e- keying management. The Application layer can also operate in standalone mode intended to debug the payload without requiring a shelf manager. ATCA-7480 Installation and Use (6806800T17A)

  • Page 283: Firmware Upgrade

    Boot POST Loader Boot Hardware Firmware Upgrade 9.2.1 HPM.1 Components All embedded software images can be upgraded via HPM.1 protocol. IPMI bootloader  IPMI firmware  IPMI FRU information   BIOS  FPGA  ATCA-7480 Installation and Use (6806800T17A)

  • Page 284: Ipmi Boot-Loader And Firmware Component

    SPI flash into the internal eNVM, depending on the boot flags indicating successful boot. The boot loader is also used as HPM.1 component; however there is no backup image. ATCA-7480 Installation and Use (6806800T17A)

  • Page 285: Iap Component

    Microsemi Inc. Its fabric can be upgraded via HPM.1 firmware upgrade. This process is referred to In Application Programming (IAP) upgrade. As there is no possibility of crisis recovery, Artesyn does not recommend to upgrade this component without any need.

  • Page 286: Bios Component

    9.2.1.4 BIOS Component The ATCA-7480 provides two SPI flashes for storing two redundant BIOS firmware images; one is called "Active", the other one is "Backup". Due to the fact that the "Active" SPI flash is routed to the Intel CPU always, the IPMC can perform HPM.1 specific firmware upgrades only to the "Backup"...
  • Page 287 : IPMI F/I Firmware Version : 0.0.00000000 BANK : J - Operational Firmware Name : PYLD FPGA Firmware Version : 0.40.0000000F BANK : K - Rollback Firmware Name : PYLD FPGA Firmware Version : 0.120.00000010 ATCA-7480 Installation and Use (6806800T17A)

  • Page 288: Firmware Upgrade Tool

    9.2.3 Firmware Upgrade Tool The primary update mechanism for the ATCA-7480 blade is the FCU tool, which is delivered with the BBS package for the blade. However, the ATCA-7480 blade family also supports upgrades with the ipmitool. Artesyn recommends to use the Pigeon Point System modified Ipmitool 1.8.13-pps2 or later versions.

  • Page 289: Updating Ipmitool

    Examples: From shelf manager:  prompt>ipmitool -t 0x92 hpm upgrade <file> with RMCP:  prompt>ipmitool -I lan -H 192.168.34.8 -U Administrator -P Administrator -t 0x92 hpm upgrade <file> ATCA-7480 Installation and Use (6806800T17A)

  • Page 290: Hpm.2 Specific Firmware Updates

    : OEM IP Address Source : Static Address IP Address : 172.16.0.221 Subnet Mask : 255.255.0.0 MAC Address : ec:9e:cd:10:a0:64 Default Gateway IP : 172.16.0.1 Default Gateway MAC : 14:14:14:14:14:14 RMCP+ Cipher Suites : 0,1,2,3 ATCA-7480 Installation and Use (6806800T17A)
  • Page 291 6|PYLD F/W | 128.02 00000003 | 128.02 00000003 | 0.02 00000003 |100%| |Upload Time: 01:40 | Image Size: 16777217 bytes --------------------------------------------------------------- ---------------- (*) Component requires Payload Cold Reset Performing activation stage: Firmware upgrade procedure successful ATCA-7480 Installation and Use (6806800T17A)

  • Page 292: Sensors

    IPMI Feature Set Sensors This section provides a description of all analog and discrete sensors available on the ATCA-7480. Table 9-2 lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose.
  • Page 293 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Hot Swap Hot Swap Sensor-specific...
  • Page 294 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Version Version Sensor-specific Change type...
  • Page 295 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm RTM 12V Voltage Threshold reading...
  • Page 296 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm OS Boot OS Boot Sensor-specific...
  • Page 297 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Boot System Boot Sensor-specific 0xFF...
  • Page 298 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm BootBank Sensor-specific 0xFF 0xFF 0x0: Boot Bank A/B...
  • Page 299 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm PWR Entry Sensor-specific [6] = VOUT_low...
  • Page 300 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Reset Source Sensor-specific [7] = IPMC Payload...
  • Page 301 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm PYLD Pwr Sensor-specific 0xFF 0xFF...
  • Page 302 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm DDR5 J15 Temp Threshold reading...
  • Page 303 IPMI Feature Set Table 9-2 ATCA-7480 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm PCH temp Temp Threshold reading...

  • Page 304: Payload Driven Sensors

    Table 9-3 Event Data of Boot Bank Sensor Event Data 1 Event Data 2 Event Data 3 bit[0] 0 = BIOS Bank A; 1 = BIOS Bank B 0xFF 0xFF bit[1] 0 = FPGA Bank A; 1 = FPGA Bank B ATCA-7480 Installation and Use (6806800T17A)

  • Page 305: Ipmc Post Results Sensor

    Hot-swap Switch State 0: Hot-swap switch is off 1: Hot-swap switch is on Bit 4 Holdup Switch State 0: Holdup Cap is not connected to -48V Out 1: Holdup Cap is connected to -48V Out ATCA-7480 Installation and Use (6806800T17A)

  • Page 306: Reset Cause Sensor

    48V Feed B Current Holdup Temp Status 0x90 IPMC Front blade Temperature Inlet LM75 private 2 0x94 IPMC Front blade Temperature Outlet LM75 private 2 0x2e IPMC Front blade Temperature DIMMs and ME Engine private 4 ATCA-7480 Installation and Use (6806800T17A)

  • Page 307: Me Power Failure Sensor

    The IPMC evaluates the Payload Power Failure Register to report power failures at the payload domain. When a Payload Power failure occurs, the red power failure LED is switched ON (signal PWR_FAIL_ is driven low). ATCA-7480 Installation and Use (6806800T17A)

  • Page 308: Payload Power Failure Cause Sensor

    EEPROM where it is stored. Once read, each section's checksum is computed and validated. IPMB-0U - Reads the ready signals coming from the I2C buffers. If this test passes, both  ready signals are active and both IPMB busses (IPMB-A and IPMB-B) are enabled. ATCA-7480 Installation and Use (6806800T17A)

  • Page 309: Ejector Handle De-Bounce

    Configuration on page 256. FRU Inventory The ATCA-7480 implements two intelligent FRUs (IPMC and MMC). Every FRU provides its own FRU information (serial, part, MAC addresses). Depending on the presence of a module, its FRU information is visible or not.

  • Page 310: Mac Address Fru Oem Records

    IPMI Feature Set The MAC addresses of a FRU are stored within the multi-record area of the FRU information. Artesyn Embedded Technologies has defined a MAC address multi-record for this purpose. For details, see MAC Address FRU OEM Records on page 310.

  • Page 311: Table 9-9 Interface Type Assignments

    IPMI Feature Set Table 9-8 Artesyn MAC Address Descriptor (continued) Offset Length Description MAC Address Count (M) (specifying a continuous pool of MAC addresses starting with the MAC address specified in this descriptor) M = 1: this descriptor specifies one MAC address M >...

  • Page 312: Reset And Power Domain

    IPMI Feature Set Reset and Power Domain The ATCA-7480 provides the following FRU instances: FRU #0: front board management and switch  FRU #1: RTM  Each FRU instance can be reset separately. Power Configuration With respect to the product version, the maximum power consumption requested by the IPMC is different.

  • Page 313: Bios Boot Configuration Parameters

    If you are reading from the storage area and you find any of these two values, your software should assume that no boot firmware options have previously been written to the storage area. ATCA-7480 Installation and Use (6806800T17A)

  • Page 314: Asynchronous Event Notification

    9.11 Serial Line Selection The ATCA-7480 provides two serial interfaces from payload. By default, the first is routed to the front connector and the second to the RTM. In addition, there is an IPMC debug interface, which can be routed either to the front or to the RTM (this function is just available if the RTM provides a serial connector at the front).

  • Page 315: Bios Boot Bank Selection

    System Boot Options Commands on page 233. 9.12.1 Boot Bank Sensor The ATCA-7480 provides a Boot Bank Sensor, illustrating from which BIOS Boot Bank the boot firmware has last booted. For details, see Boot Bank Supervision Sensor on page 304.

  • Page 316: Fail Safe Logic

    BMC watchdog expires, the IPMI management controller will swap the boot banks before resetting the CPU. Thus the blade can recover by booting from its redundant boot flash, which contains the old active firmware image, which did work before firmware upgrade. ATCA-7480 Installation and Use (6806800T17A)

  • Page 317: Figure 9-3 Failsafe

    Swap Boot Bank and send a Failsafe count < 3? System Firmware Hang event to the ShMM Reboot the blade Failsafe in general can recover from scenarios: Missing or defect boot block  Firmware image has a bad checksum  ATCA-7480 Installation and Use (6806800T17A)

  • Page 318: Glue Logic Fpga Flash Selection

    By default, Failsafe is disabled. 9.13 Glue Logic FPGA Flash Selection The ATCA-7480 provides redundant FPGA flashes for both manual and automatic crisis recoveries. The general concept is that there is always an active and a standby SPI flash device. The role of these two devices can be reversed by the IPMC;...

  • Page 319: Boot Bank Sensor

    System Boot Options Commands on page 233. 9.13.1 Boot Bank Sensor The ATCA-7480 provides a Boot Bank Sensor, illustrating from which FPGA Bank the FPGA has booted last. For details, see Boot Bank Supervision Sensor on page 304.
  • Page 320 System Firmware FPGA Done Hang event to the ShMM Both FPGA banks corrupted Set failprotect to FAILED_TWICE Present? Remote Crisis Recovery Mode (M1) FPGA Load Done Swap Boot Bank to protect working image Success ATCA-7480 Installation and Use (6806800T17A)

  • Page 321: Remote Crisis Recover Mode

    The IPMI command, Set/Get System Boot Options together with the OEM parameter #98 can be used to specify the timeout for Graceful Shutdown persistently. For details, see System Boot Options Commands on page 233. By default, Graceful Shutdown persistently value is set to 10 seconds. ATCA-7480 Installation and Use (6806800T17A)

  • Page 322: Local System Event Log (Sel)

    9.15 Local System Event Log (SEL) The ATCA-7480 IPMC supports a local SEL. The local SEL size is configured to hold 1K entries in a circular FIFO buffer. Once the circular buffer is full, the next SEL entry will overwrite the oldest SEL entry in the buffer.

  • Page 323: Replacing The Battery

    Some blade variants contain an on-board battery. Its location is shown in the following figure. A battery-less variant based on SUPERCAP is available on demand. Figure A-1 Location of On-board Battery Battery/ Goldcap J11 DIMM 1 ZONE 1 ATCA-7480 Installation and Use (6806800T17A)
  • Page 324 The battery provides data retention of seven years summing up all periods of actual data use. Artesyn Embedded Technologies therefore assumes that there is usually no need to replace the battery except, for example, in case of long-term spare part handling.
  • Page 325 Removing the battery with a screw driver may damage the PCB or the battery holder. To prevent this damage, do not use a screw driver to remove the battery from its holder. 2. Install the new battery following the "positive" and "negative" signs. ATCA-7480 Installation and Use (6806800T17A)
  • Page 326 Replacing the Battery ATCA-7480 Installation and Use (6806800T17A)

  • Page 327: Related Documentation

    The publications listed below are referenced in this manual. You can obtain electronic copies of Artesyn Embedded Technologies - Embedded Computing publications by contacting your local Artesyn sales office. For released products, you can also visit our Web site for the latest copies of our product documentation.

  • Page 328: Manufacturers' Documents

    PCI-SIG PCI Local Bus Specification Revision 2.2 PCI-X Addendum to the PCI Local Bus Specification 1.0 PICMG PICMG 3.0 Revision 2.0 Advanced TCA Base Specification PICMG 3.1 Revision 1.0 Specification Ethernet/Fiber Channel for AdvancedTCA Systems ATCA-7480 Installation and Use (6806800T17A)
  • Page 330 Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners. © 2015 Artesyn Embedded Technologies, Inc.

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