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EM8551B Terminal Function
Pin
Port Name
Symbol
No.
1
A1
CVBS
2
A2
AVDD_CVBS
3
A3
AVSS_CVBS
4
A4
AVDD_VDAC
5
A5
VID_D[23]
6
A6
VID_D[17]
7
A7
VID_D[12]
8
A8
VID_CLKOUT
9
A9
VID_D[6]
10
A10
VID_D[2]
11
A11
VID_HSYNC
12
A12
PIO1[2]
13
A13
BREAKPT
14
A14
DBGACK
15
A15
DBGRQ
16
A16
TRST#
17
A17
TMS
18
A18
TDO
19
A19
TDI
20
A20
TCK
21
A21
PWRDWN#
22
A22
XIN
23
A23
XOUT
24
A24
CLKOUT
25
A25
UART_CLKIN
26
A26
PIO0[11]
27
A27
PIO0[12]
28
B1
Y
29
B2
AVDD_Y
30
B3
AVSS_Y
31
B4
AVSS_VDAC
32
B5
VID_D[16]
33
B6
VID_D[18]
34
B7
VID_D[13]
35
B8
VID_D[9]
36
B9
VID_CLKIN
37
B10
VID_D[3]
38
B11
VID_DVLD
39
B12
PIO1[1]
40
B13
PIO1[5]
41
B14
PIO1[9]
42
B15
PIO1[10]
43
B16
PIO1[8]
44
B17
PIO1[15]
45
B18
UART0_DTR#
46
B19
UART0_DSR#
47
B20
NC
48
B21
PIO0[0]
49
B22
PIO0[5]
50
B23
PIO0[7]
51
B24
PIO0[9]
52
B25
PIO0[14]
53
B26
PIO0[15]
54
B27
SM_D[0]
55
C1
U
56
C2
AVDD_U
57
C3
AVSS_U
58
C4
RSET
59
C5
VID_D[19]
60
C6
VID_D[20]
61
C7
VID_D[14]
62
C8
VID_D[10]
63
C9
VID_D[7]
64
C10
VID_D[4]
65
C11
VID_D[0]
66
C12
PIO1[0]
67
C13
PIO1[4]
68
C14
PIO1[7]
69
C15
PIO1[11]
Description
Analog Video Output CVBS
VDD3_3CVBS
VSS_CVBS
VDD3_3DAC
-
-
Video Output:C[4]
Video Output:Video(Pixel) clock out
Video Output:Y[6]
Video Output:Y[2]
Video Output Horizontal sync
Programmable I/O Port 1 Bit 2
DEBUG IF:Breakpoint
DEBUG IF:Debug Acknowledge
DEBUG IF:Debug Request
JTAG:Test Reset
JTAG:Test Mode Select
JTAG:Test Data Output
JTAG:Test Data Input
JTAG:Test Clock Input
PowerDown/PLL Enable
27MHz crystal oscillator input
27MHz crystal oscillator output
27MHz internal Oscillator
output(bufferd)
Receive Clock for UART 0 and 1
Programmable I/O Port 0 Bit 11
Programmable I/O Port 0 Bit 12
Analog video output Y
VDD3_3Y
VSS_Y
VSS_DAC
-
-
Video Output:C[5]
Video Output:C[1]
Video Output:Video Clock In
Video Output:Y[3]
Video Output:Video active/Video valid
Programmable I/O Port 1 Bit 1
Programmable I/O Port 1 Bit 5
Programmable I/O Port 1 Bit 9
Programmable I/O Port 1 Bit 10
Programmable I/O Port 1 Bit 8
Programmable I/O Port 1 Bit 15
UART0:Data Terminal Ready
UART0:Data Set Ready
Programmable I/O Port 0 Bit 0
Programmable I/O Port 0 Bit 5
Programmable I/O Port 0 Bit 7
Programmable I/O Port 0 Bit 9
Programmable I/O Port 0 Bit 14
Programmable I/O Port 0 Bit 15
System Memory Data Bit0
Analog Video output U
VDD3_3_U
VSS U
-
-
-
Video Output:C[6]
Video Output:C[2]
Video Output:Y[7]
Video Output:Y[4]
Video Output:Y[0]
Programmable I/O Port 1 Bit 0
Programmable I/O Port 1 Bit 4
Programmable I/O Port 1 Bit 7
Programmable I/O Port 1 Bit 11
I/O
Det
Ext
Res
Ini
O
-
-
-
-
Ext video buffer(BH7862) ganerates composite
video.
-
-
-
-
-
Connect to 3.3V_A(for Video DAC)
-
-
-
-
-
Connect to GND_A(for Video DAC)
-
-
-
-
-
Connect to 3.3V_A(for Video DAC)
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
I
Lev
Pu
H
H
L:Active
I
-
GND
L
L
Connect to GND_D
O
-
-
-
-
Not used
I
-
GND
L
L
Not used
I
-
GND
L
L
Not used
I
-
GND
L
L
Not used
O
-
-
-
-
Not used
I
-
GND
L
L
Not used
I
-
A24
-
-
Connect to 27M(A24[24])
-
-
3.3V_D
H
H
Connect to 3.3V_D(PLL Enable)
I
-
-
-
-
Connect to X'tal for system clock
O
-
-
-
-
Connect to X'tal for system clock
O
-
-
-
-
27M clock is used for -DTACK/RDY signal
generating.
(I)
-
intPd
-
-
Not used
I
Lev
Pu
H/L
H/L
L:Active
I
Lev
Pu
H/L
H/L
L:Active
O
-
-
-
-
Connect to video buffer(BH7862:YIN and PYIN)
-
-
-
-
-
Connect to 3.3V_A(for Video DAC)
-
-
-
-
-
Connect to GND_A(for Video DAC)
-
-
-
-
-
Connect to GND_A(for Video DAC)
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
-
-
-
-
-
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
I
Lev
Pu
H/L
H/L
L:Active
O
-
Pd
L
L
H:Active
O
-
-
H
H
for Ethernet(DM9000) H:Active
O
-
Pu
H
H
for IDE/PC card L:Active
O
-
Pd
L
L
L:Active(mute on)/H:Mute off
O
-
-
-
-
Control signal for rtc(RTC4543)
(O)
-
-
-
-
Not used
(I)
-
intPd
-
-
Not used
-
-
-
-
-
Not used
I
Lev
Pu
H/L
H/L
L:Time set mode/H:Normal mode
I
Lev
Pu
H/L
H/L
L:Active
I
Ed
Pu
H/L
H/L
H to L:Pc card inserted/L to H:Pc card ejected
I
Lev
Pu
H/L
H/L
L:Active
I
Lev
Pu
H/L
H/L
L:Active
I
Lev
Pu
H/L
H/L
L:Active
I/O
-
-
-
-
Connect to system sdram(D0) and flash chip(D0)
O
-
-
-
-
Connect to video buffer(BH7862:PBIN)
-
-
-
-
-
Connect to 3.3V_A(for Video DAC)
-
-
-
-
-
Connect to GND_A(for Video DAC)
-
-
-
-
-
200ohm terminated(single termination)
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
(O)
-
-
-
-
Not used
I
Lev
Pu
H/L
H/L
L:Active
O
-
Pd
L
L
H:Active
O
-
Pd
L
L
H:Active
I
-
-
H/L
H/L
Connect to RTC 1Hz output
7
DN-V750/V755
Function
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