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E2* Core IP Series
SiFive E2* Core IP Series Manuals
Manuals and User Guides for SiFive E2* Core IP Series. We have
1
SiFive E2* Core IP Series manual available for free PDF download: User Manual
SiFive E2* Core IP Series User Manual (41 pages)
FPGA Eval Kit
Brand:
SiFive
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Sifive Core IP FPGA Eval Kit User Guide
3
Table of Contents
5
List of Figures
7
1 Introduction
9
About this Document
9
About this Release
9
Evaluation Version Limitations
9
2 Required Hardware
11
Xilinx Arty A7 Artix-7 FPGA Evaluation Kit
11
USB a to Micro-B Cable
11
Olimex ARM-USB-TINY-H Debugger
11
USB a to B Cable
11
Male-To-Female Jumper Cables (10)
12
3 Board Setup
13
Connecting the USB Interface
13
Connecting the Debugger
13
Debugging Connections between Olimex ARM-USB-TINY-H and Arty Board's PMOD Header JD
14
Debug Connections to the Olimex ARM-USB-TINY-H
14
Debug Connections to the Arty Board JD PMOD Header
14
Photo of the Arty Board Showing USB and Debug Connections
15
4 FPGA Flash Programming File
17
Programming the Arty 35T SPI Flash
17
Programming the Arty 100T SPI Flash
18
5 Boot and Run
19
Serial Setup
19
Reset and Boot
21
Load a Program
21
Default Demo Program
21
Terminal Log
21
6 Software Development Flow
23
Supported Platforms
23
Software Development Using Freedom Studio IDE
23
Software Development Using Freedom E SDK Command Line Tools
23
Setting up Freedom-E-SDK
24
Cloning the Repository
24
Freedom E SDK Arty BSP
25
Example Programs
25
Using the Freedom E SDK
26
Building an Example
26
Uploading to the Target Board
26
Debugging a Target Program
27
Cleaning a Target Program Build Directory
27
Create a Standalone Project
27
Core IP FPGA Eval Kit Memory Map
29
Core IP FPGA Eval Kit Clock and Reset
29
Core IP FPGA Eval Kit Pinout
29
7 E2 Core IP FPGA Eval Kit MCS Image Contents
29
E2 Core IP FPGA Eval Kit Block Diagram
30
8 E3 / S5 Core IP FPGA Eval Kit MCS Image Contents
33
Core IP FPGA Eval Kit Memory Map
33
Core IP FPGA Eval Kit Clock and Reset
33
Core IP FPGA Eval Kit Pinout
33
E3 / S5 Core IP FPGA Eval Kit Block Diagram
34
9 E7 / S7 MCS Image Contents
37
Core IP FPGA Eval Kit Memory Map
37
Core IP FPGA Eval Kit Clock and Reset
37
Core IP FPGA Eval Kit Pinout
37
E7 / S7 Core IP FPGA Eval Kit Block Diagram
38
10 For more Information
41
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